Datenblatt-Suchmaschine für elektronische Bauteile |
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FAN3278T Datenblatt(PDF) 3 Page - Fairchild Semiconductor |
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FAN3278T Datenblatt(HTML) 3 Page - Fairchild Semiconductor |
3 / 15 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3278 • Rev. 1.0.0 3 Pin Configuration Figure 3. Pin Configuration (Top View) Thermal Characteristics (1) Package JL (2) JT (3) JA (4) JB (5) JT (6) Unit 8-Pin Small-Outline Integrated Circuit (SOIC) 40 31 89 43 3 °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB ( JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT ( JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. Pin Definitions Pin# Name Description 1 ENA Enable Input for Channel A . Pull pin LOW to inhibit driver A. ENA has TTL thresholds. 8 ENB Enable Input for Channel B . Pull pin LOW to inhibit driver B. ENB has TTL thresholds. 3 GND Ground . Common ground reference for input and output circuits. 2 INA Input to Channel A . 4 INB Input to Channel B . 7 OUTA Gate Drive Output A : Held LOW unless required input is present and VDD is above the internal voltage threshold where the IC is functional. 5 OUTB Gate Drive Output B (inverted from the input). Held HIGH unless the required input is present and VDD is above the internal voltage threshold where the IC is functional. 6 VDD Supply Voltage . Provides power to the IC. |
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