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FAN3121T Datenblatt(PDF) 7 Page - Fairchild Semiconductor |
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FAN3121T Datenblatt(HTML) 7 Page - Fairchild Semiconductor |
7 / 15 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3278 • Rev. 1.0.0 7 Electrical Characteristics (Continued) Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device (Isink) and negative out of the device (Isource). Symbol Parameter Conditions Min. Typ. Max. Unit Output IPK_OFF OUT Current, Peak, Turn-Off (10) CLOAD=0.1µF, f=1kHz 1.5 A IPK_ON OUT Current, Peak, Turn-On (10) CLOAD=0.1µF, f=1kHz -1.0 A IOFF OUT Current, Mid-Voltage, Turn-Off (10 OUT at VDD, CLOAD=0.1µF, f=1kHz 1.0 A ION OUT Current, Mid-Voltage, Turn-On (10) OUT at VDD/2, CLOAD=0.1µF, f=1kHz -0.5 A VOUTA OUTA Drive Voltage VDD=27V, INA=“HI” 11 13 V VOUTB OUTB Drive Voltage, VDD – VOUTB VDD=27V, INA=“HI” 11 13 V VOUTA OUTA Drive Voltage VDD=10V, INB=“HI” 6.5 7.0 V VOUTB OUTB Drive Voltage, VDD – VOUTB VDD=10V, INB=“HI” 6.5 7.0 V RO_A_SINK OUTA Sink Impedance (Turn-Off) (10) VDD=6V, CLOAD=0.1µF 4.2 Ω RO_A_SRC OUTA Source Impedance (Turn-On) (10) VDD=6V, CLOAD=0.1µF 10.3 Ω RO_B_SINK OUTB Sink Impedance (Turn-On) (10) VDD=6V, CLOAD=0.1µF 6.8 Ω RO_B_SRC OUTB Source Impedance (Turn-Off) (10) VDD=6V, CLOAD=0.1µF 13.7 Ω tON,N Output A Rise Time (11) CLOAD=1000pF to GND 17 30 ns tOFF,N Output A Fall Time (11) CLOAD=1000pF to GND 8 15 ns tON,P Output B Fall Time (11) CLOAD=1000pF to VDD 21 30 ns tOFF,P Output B Rise Time (11) CLOAD=1000pF to VDD 8 15 ns tD1 Output Propagation Delay On (11) 0 - 5VIN, 1V/ns Slew Rate 45 70 ns tD2 Output Propagation Delay Off (11) 0 - 5VIN, 1V/ns Slew Rate 35 60 ns IRVS Output Reverse Current Withstand (10) 500 mA Notes: 8. The internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8V to 27V. The FAN3278 can be driven from a voltage rail of less than 8V; however, with reduced gate drive current. 9. EN inputs have near-TTL thresholds (refer to the ENABLE section). 10. Not tested in production. 11. See the Timing Diagrams of Figure 5 and Figure 6. |
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