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FAN6208 Datenblatt(PDF) 6 Page - Fairchild Semiconductor

Teilenummer FAN6208
Bauteilbeschribung  Secondary-Side Synchronous Rectifier Controller
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN6208 Datenblatt(HTML) 6 Page - Fairchild Semiconductor

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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6208 • Rev. 1.0.1
6
Electrical Characteristics
VDD=20V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Gate Section
VZ1 VZ2
Gate Output Voltage
Maximum (Clamping)
VDD=20V
10
12
14
V
VOL1 VOL2
Gate Output Voltage LOW
VDD=12V; IO=100mA
0.5
V
VOH1VOH2
Gate Output Voltage HIGH VDD=12V; IO=100mA
9
V
tR1 tR2
Rising Time
VDD=12V; CL=6nF;
VGATE=2V to 9V
30
70
120
ns
tF1 tF2
Falling Time
VDD=12V; CL=6nF;
VGATE=9V to 2V
30
50
70
ns
tPD_HIGH_DETL1
tPD_HIGH_DETL2
Propagation Delay to Gate
Output HIGH (DETL
Trigger)
tR: 0V~2V, VDD=12V
(DET Floating)
120
ns
tPD_LOW_ DETL1
tPD_LOW_ DETL2
Propagation Delay to Gate
Output LOW (DETL
Trigger)
tF: 100%~90%, VDD=12V
(DET Floating)
120
ns
tON_MAX1
tON_MAX2
Maximum On-Time
Trim Maximum On-Time
9.0
10.5
12.0
μs
tINHIBIT_LF1
tINHIBIT_LF2
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
VRP < 1.5V
1.8
2.1
2.5
μs
tINHIBIT_HF1
tINHIBIT_HF2
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
VRP > 1.5V
1.25
1.45
1.70
μs
tBLANKING1
tBLANKING2
Blanking Time for SR Turn-
Off Triggered by DETL
High (Minimum On-Time)
300
ns
KR
Gate ON-Time Increase
Rate Between Two
Consecutive Cycles
tON(n) / tON(n-1) %
140
%
Timing Estimator Section
tDW
Detection Window for
Insufficient Dead Time
(from Gate Turn-Off to
DETL HIGH)
80
125
150
ns
tSHRINK-DT
Gate Shrink Time by
Insufficienct Dead Time
RRP=20KΩ, tDETL=5μs
1.00
1.25
1.50
μs
tDEAD
Dead Time by Timing
Estimator (70kHz ~
140kHz, VRP < 1.5V)
tDETL=4μs, RRP=20KΩ
210
300
390
ns
tDETL=6μs, RRP=20KΩ
570
720
870
Dead Time by Timing
Estimator (160kHz ~
240kHz, VRP > 1.5V)
tDETL=2.5μs, RRP=43KΩ
220
320
420
tDETL=3.8μs, RRP=43KΩ
560
670
780
tDB
DETL HIGH-to-LOW
Debounce Time for Gate
Turn-on Trigger
150
ns
tSHRINK-RNG
Gate Shrink by DETL
Ringing around Zero
1.2
μs
tGreen_DH
DETL Pull-HIGH Time
Threshold for Green Mode
18
24
30
μs
Continued on the following page…


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