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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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MC68360ZP25 Datenblatt(PDF) 10 Page - Motorola, Inc |
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MC68360ZP25 Datenblatt(HTML) 10 Page - Motorola, Inc |
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10 / 962 page  Table of Contents Paragraph Title Page Number Number vi MC68360 USER’S MANUAL MOTOROLA 5.5.4.1 Four-Word Stack Frame ........................................................................5-56 5.5.4.2 Six-Word Stack Frame...........................................................................5-56 5.5.4.3 Bus Error Stack Frame ..........................................................................5-56 5.6 Development Support ............................................................................5-59 5.6.1 CPU32+ Integrated Development Support ............................................5-59 5.6.1.1 Background Debug Mode (BDM) Overview...........................................5-59 5.6.1.2 Deterministic Opcode Tracking Overview..............................................5-60 5.6.1.3 On-Chip Hardware Breakpoint Overview...............................................5-60 5.6.2 Background Debug Mode ......................................................................5-60 5.6.2.1 Enabling BDM ........................................................................................5-60 5.6.2.2 BDM Sources.........................................................................................5-61 5.6.2.2.1 External BKPT Signal ............................................................................5-62 5.6.2.2.2 BGND Instruction ...................................................................................5-62 5.6.2.2.3 Double Bus Fault ...................................................................................5-62 5.6.2.3 Entering BDM.........................................................................................5-62 5.6.2.4 Command Execution..............................................................................5-62 5.6.2.5 BDM Registers.......................................................................................5-63 5.6.2.5.1 Fault Address Register (FAR)................................................................5-63 5.6.2.5.2 Return Program Counter (RPC).............................................................5-63 5.6.2.5.3 Current Instruction Program Counter (PCC)..........................................5-63 5.6.2.6 Returning from BDM ..............................................................................5-63 5.6.2.7 Serial Interface.......................................................................................5-63 5.6.2.7.1 CPU Serial Logic....................................................................................5-65 5.6.2.7.2 Development System Serial Logic .........................................................5-66 5.6.2.8 Command Set ........................................................................................5-68 5.6.2.8.1 Command Format ..................................................................................5-68 5.6.2.8.2 Command Sequence Diagram...............................................................5-69 5.6.2.8.3 Command Set Summary........................................................................5-69 5.6.2.8.4 Read A/D Register (RAREG/RDREG)...................................................5-71 5.6.2.8.5 Write A/D Register (WAREG/WDREG) .................................................5-71 5.6.2.8.6 Read System Register (RSREG)...........................................................5-71 5.6.2.8.7 Write System Register (WSREG) ..........................................................5-72 5.6.2.8.8 Read Memory Location (READ) ............................................................5-73 5.6.2.8.9 Write Memory Location (WRITE) ...........................................................5-74 5.6.2.8.10 Dump Memory Block (DUMP)................................................................5-75 5.6.2.8.11 Fill Memory Block (FILL) ........................................................................5-76 5.6.2.8.12 Resume Execution (GO)........................................................................5-77 5.6.2.8.13 Call User Code (CALL) ..........................................................................5-77 5.6.2.8.14 Reset Peripherals (RST)........................................................................5-79 5.6.2.8.15 No Operation (NOP) ..............................................................................5-79 5.6.2.8.16 Future Commands .................................................................................5-80 5.6.3 Deterministic Opcode Tracking..............................................................5-80 5.6.3.1 Instruction Fetch (IFETCH) ....................................................................5-80 5.6.3.2 Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80 5.6.3.3 Opcode Tracking during Loop Mode......................................................5-82 |
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