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LS3958_PDIP Datenblatt(PDF) 1 Page - Micross Components

Teilenummer LS3958_PDIP
Bauteilbeschribung  Monolithic Dual N-Channel JFET
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Hersteller  MICROSS [Micross Components]
Direct Link  http://www.micross.com
Logo MICROSS - Micross Components

LS3958_PDIP Datenblatt(HTML) 1 Page - Micross Components

  LS3958_PDIP Datasheet HTML 1Page - Micross Components  
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Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
FEATURES 
LOW DRIFT 
|∆ VGS1‐2 /∆T|= 5µV/°C max.
LOW LEAKAGE 
IG = 20pA TYP. 
LOW NOISE 
en = 10nV/√Hz TYP. 
ABSOLUTE MAXIMUM RATINGS  
@ 25°C (unless otherwise noted) 
Maximum Temperatures 
Storage Temperature ‐65°C to +200°C 
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor – Note 1 
‐VGSS 
Gate Voltage to Drain or Source 
60V 
‐VDSO 
Drain to Source Voltage 
60V 
‐IG(f) 
Gate Forward Current 
50mA 
Maximum Power Dissipation 
Device Dissipation @ Free Air – Total                 400mW @ 25°C 
 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL 
CHARACTERISTICS 
VALUE 
UNITS 
CONDITIONS 
| V GS1‐2 / T| max. 
DRIFT VS. 
TEMPERATURE 
100 
µV/°C 
VDG=20V, ID=200µA 
TA=‐55°C to +125°C 
| V GS1‐2 | max. 
OFFSET VOLTAGE 
25 
mV 
VDG=20V, ID=200µA 
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
CHARACTERISTICS 
MIN. 
TYP. 
MAX. 
UNITS 
CONDITIONS 
BVGSS 
Breakdown Voltage 
60 
‐‐ 
‐‐ 
VDS = 0                  ID=1µA 
BVGGO 
Gate‐To‐Gate Breakdown 
60 
‐‐ 
‐‐ 
      I G= 1nA               ID= 0               IS= 0 
 
YfSS 
TRANSCONDUCTANCE 
Full Conduction 
 
1000 
 
2000 
 
3000 
 
µmho 
 
VDG= 20V         VGS= 0V      f = 1kHz 
YfS 
Typical Operation 
500 
700 
1000 
µmho 
     VDG= 20V         ID= 200µA     
|YFS1‐2 / Y FS| 
Mismatch 
‐‐ 
0.6 
%  
 
IDSS 
DRAIN CURRENT 
Full Conduction 
 
0.5 
 
 
 
mA 
 
VDG= 20V              VGS= 0V 
|IDSS1‐2 / IDSS| 
Mismatch at Full Conduction 
‐‐ 
%  
 
VGS(off) or Vp 
GATE VOLTAGE 
Pinchoff voltage 
 
 
 
4.5 
 
 
VDS= 20V               ID= 1nA 
VGS(on) 
Operating Range 
0.5 
‐‐ 
              VDS=20V                 ID=200µA 
 
‐IG 
GATE CURRENT 
Operating 
 
‐‐ 
 
20 
 
50 
 
pA 
 
VDG= 20V          ID= 200µA 
‐IG 
High Temperature 
‐‐ 
‐‐ 
50 
nA 
TA= +125°C
 
‐IG 
Reduced  VDG 
‐‐ 
‐‐ 
pA 
VDG= 10V         ID= 200µA 
‐IGSS 
At Full Conduction 
‐‐ 
‐‐ 
100 
pA 
VDG= 20V              VDS= 0 
 
YOSS 
OUTPUT CONDUCTANCE 
Full Conduction 
 
‐‐ 
 
‐‐ 
 
 
µmho 
 
VDG= 20V              VGS= 0V 
YOS 
Operating 
‐‐ 
0.1 
µmho 
VDG=  20V           ID= 200µA 
|YOS1‐2
Differential 
‐‐ 
0.01 
0.1 
µmho 
 
CMR 
COMMON MODE REJECTION 
‐20 log | VGS1‐2/ VDS
 
‐‐ 
 
100 
 
‐‐ 
 
dB 
 
∆VDS = 10 to 20V        ID=200µA 
CMR ‐20 log | VGS1‐2/ VDS
‐‐ 
75 
‐‐ 
dB ∆VDS = 5 to 10V        ID=200µA 
 
NF 
NOISE 
Figure 
 
‐‐ 
 
‐‐ 
 
0.5 
 
dB 
VDS= 20V      VGS= 0V       RG= 10MΩ 
f= 100Hz           NBW= 6Hz 
en 
Voltage 
‐‐ 
‐‐ 
15 
nV/√Hz 
VDS=20V   ID=200µA   f=10Hz  NBW=1Hz 
 
CISS 
CAPACITANCE 
Input 
 
‐‐ 
 
‐‐ 
 
 
pF 
 
VDS= 20V       VGS= 0V       f= 1MHz 
CRSS 
Reverse Transfer 
‐‐ 
‐‐ 
pF 
CDD 
Drain‐to‐Drain 
‐‐ 
0.1 
‐‐ 
pF 
VDG=  20V           ID= 200µA 
The LS3958 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
LS3958
MONOLITHIC DUAL
N-CHANNEL JFET
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
LS3958 Applications:
Wideband Differential Amps
High Input Impedance Amplifiers
The LS3958 family are matched JFET pairs for
differential amplifiers. The LS3958 family of general
purpose JFETs is characterized for low and medium
frequency differential amplifiers requiring low offset
voltage, drift, noise and capacitance
The LS3958 family exhibits low capacitance - 6pF max
and a spot noise figure of - 0.5dB max. The part offers
a superior tracking ability.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
PDIP / SOIC (Top View)
Available Packages:
LS3958 in PDIP / SOIC
LS3958 available as bare die
Please contact Micross for full package and die dimensions
Micross Components Europe
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution


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