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5V49EE504NLGI8 Datenblatt(PDF) 5 Page - Integrated Device Technology |
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5V49EE504NLGI8 Datenblatt(HTML) 5 Page - Integrated Device Technology |
5 / 29 page IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 5 IDT5V49EE504 REV F 022310 PLL Features and Descriptions PLL0 Block Diagram PLL1, PLL2 and PLL3 Block Diagram VCO N D A Sigma-Delta Modulator 12-bit 7-bit 4-bit VCO N D 12-bit 7-bit Pre-Divider (D)1 Values Multiplier (M)2 Values Programmable Loop Bandwidth Spread Spectrum Generation Capability PLL0 1 - 127 10 - 8206 Yes Yes PLL1 1 - 127 1 - 4095 Yes No PLL2 1 - 127 1 - 4095 Yes No PLL3 3 - 127 12 - 4095 Yes Yes 1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use) 2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N. |
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