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TMP320LF2401AVFS Datenblatt(PDF) 1 Page - Texas Instruments |
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TMP320LF2401AVFS Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 88 page TMS320LF2401A, TMS320LC2401A DSP CONTROLLERS SPRS161K − MARCH 2001 − REVISED JULY 2007 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D High-Performance Static CMOS Technology − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.3-V Design D Based on TMS320C2xx DSP CPU Core − Code-Compatible With 240x and F243/F241/C242 − Instruction Set Compatible With F240 D On-Chip Memory − Up to 8K Words x 16 Bits of Flash EEPROM (2 Sectors) (LF2401A) − 8K Words x 16 Bits of ROM (LC2401A) − Programmable “Code-Security” Feature for the On-Chip Flash/ROM − Up to 1K Words x 16 Bits of Data/Program RAM − 544 Words of Dual-Access RAM − Up to 512 Words of Single-Access RAM D Boot ROM − SCI Bootloader D Event-Manager (EV) Module (EVA), Which Includes: − Two 16-Bit General-Purpose Timers − Seven 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable: − Three-Phase Inverter Control − Center- or Edge-Alignment of PWM Channels − Emergency PWM Channel Shutdown With External PDPINTA Pin − Programmable Deadband (Deadtime) Prevents Shoot-Through Faults − One Capture Unit for Time-Stamping of External Events − Input Qualifier for Select Pins − Synchronized A-to-D Conversion − Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control D Small Foot-Print (7 mm × 7 mm) Ideally Suited for Space-Constrained Applications D Watchdog (WD) Timer Module D 10-Bit Analog-to-Digital Converter (ADC) − 5 Multiplexed Input Channels − 500 ns Minimum Conversion Time − Selectable Twin 8-State Sequencers Triggered by Event Manager D Serial Communications Interface (SCI) D Phase-Locked-Loop (PLL)-Based Clock Generation D Up to 13 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins D User-Selectable Dual External Interrupts (XINT1 and XINT2) D Power Management: − Three Power-Down Modes − Ability to Power Down Each Peripheral Independently D Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1† (JTAG) D Development Tools Include: − Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger − Evaluation Modules − Scan-Based Self-Emulation (XDS510 ) − Broad Third-Party Digital Motor Control Support D 32-Pin VF Low-Profile Quad Flatpack (LQFP) D Extended Temperature Options (A and S) − A: − 40 °C to 85°C − S: − 40 °C to 125°C Copyright 2007, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio and XDS510 are trademarks of Texas Instruments. All trademarks are the property of their respective owners. † IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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