4

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FN6189.4

December 17, 2010

SDA, SCL Input Logic High

V

SDA, SCL Input Logic Low

0.55

V

SDA, SCL Hysteresis

(Note 9)

260

mV

SDA Output Logic High

V

SDA Output Logic Low

@ 3mA

0.4

V

WP Input Logic High

V

WP Input Logic Low

V

WP Hysteresis

(Note 9)

V

WP Input Current

0.20

35

µA

SCL Clock Frequency

0

400

kHz

0.6

µs

1.3

µs

050

ns

100

ns

900

ns

Dependent on Load (Note 10)

20 + 0.1*Cb

1000

ns

(Note 10)

20 + 0.1*Cb

300

ns

200

µs

0.6

µs

0.6

µs

0.6

µs

Cb

400

pF

SDA Pin Capacitance

10

pF

SCL Pin Capacitance

10

pF

EEPROM Write Cycle Time

100

ms

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

9. Simulated and Determined via Design and NOT Directly Tested.

11. A typical Current of 20

Equation 2 on page 5 with Setting = 128.

Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

(Note 6)

TYP

MAX

(Note 6) UNITS

ISL45041