BA□□JC5 Series,BA00JC5WT

Technical Note

8/10

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2011.02 - Rev.B

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VCC

Output pin

Back current prevention diode

Bypass Diode



Notes for use

1.

Absolute maximum ratings

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,

can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit.

If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such

as fuses.

2.

GND voltage

The potential of GND pin must be minimum potential in all operating conditions.

3.

Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

4.

Inter-pin shorts and mounting errors

Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any

connection error or if pins are shorted together.

5.

Actions in strong electromagnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.

6.

Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to

stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting

it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an

antistatic measure. Use similar precaution when transporting or storing the IC.

7.

Regarding input pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated.P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example, the relation between each potential is as follows:

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes

operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should

8.

Ground Wiring Pattern

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,

placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage

variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change

the GND wiring pattern of any external components, either.

9.

Thermal shutdown circuit

The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is

designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation.

Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this

circuit is assumed.

10. Overcurrent Protection Circuit

An overcurrent protection circuit is incorporated in order to prevention destruction due to short-time overload currents.

Continued use of the protection circuits should be avoided. Please note that the current increases negatively impact the temperature.

11. Damage to the internal circuit or element may occur when the polarity of the Vcc pin is opposite to that of the other pins in

applications. (I.e. Vcc is shorted with the GND pin while an external capacitor is charged.) Use a maximum capacitance

of 1000μF for the output pins. Inserting a diode to prevent back-current flow in series with Vcc or bypass diodes

between Vcc and each pin is recommended.

Parasitic element

Fig. 21 Bypass Diode

Fig. 22 Example of Simple Bipolar IC Architecture

(Pin A)

GND

Parasitic element

GND

(Pin B)

B

C

E

Parasitic elements or

transistors

GND

P 基板

N

P

N

N

（端子

A）

抵抗

GND

Ｎ

Ｐ

N

Ｎ

（端子

B）

トランジスタ

(NPN)

B

N

E

C

GND

P 基板

寄生素子

Transistor (NPN)

Resistor

（

Pin A）

P substrate

Parasitic element

（

Pin B）

N

P

N

P substrate

N