Datenblatt-Suchmaschine für elektronische Bauteile |
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GS1540 Datenblatt(PDF) 8 Page - Gennum Corporation |
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GS1540 Datenblatt(HTML) 8 Page - Gennum Corporation |
8 / 17 page GENNUM CORPORATION 522 - 27 - 03 8 of 17 72 LFA_VCC Power Input Positive Supply. Loop filter most positive power supply connection. 73 LFA Analog Output Control Signal Output. Control voltage for GO1515 VCO. 74 LBCONT Analog Input Control Signal Input. Used to provide electronic control of Loop Bandwidth. 75 LFA_VEE Power Input Negative Supply. Loop filter most negative power supply connection. 76 DFT_VEE Power Input Most negative power supply connection - enables the jitter demodulator functionality. This pin should be connected to ground. If left floating, the DM function is disabled resulting in a current saving of 340µA. 79, 80 DM, DM Analog Output Test Signal. Used for manufacturing test only. These pins must be floating for normal operation. 81, 85 LFS, LFS Analog Input Loop Filter Connections. 86 IJI Analog Output Status Signal Output. Approximates the amount of excessive jitter on the incoming DDI and DDI input. 89 VCO Analog Input Control Signal Input. Input pin is AC coupled to ground using a 50 Ω transmission line. 91 VCO Analog Input Control Signal Input. Voltage controlled oscillator input. This pin is connected to the output pin of the GO1515 VCO. This pin must be connected to the GO1515 VCO output pin via a 50 Ω transmission line. 93, 96 PLCAP, PLCAP Analog Input Control Signal Input. Phase lock detect time constant capacitor. 98 PLL_LOCK TTL Output Status Indicator Signal. This signal is a combination (logical AND) of the carrier detect and phase lock signals. When input is present and PLL is locked, the PLL_LOCK goes high and the outputs are valid. When the PLL_LOCK output is low the data output is muted (latched at the last state). PLL_LOCK is independent of the BYPASS signal. 105 BYPASS TTL Input Control Signal Input. Selectable input that controls whether the input signal is reclocked or passed through the chip. When BYPASS is high; the input signal is reclocked. When BYPASS is low; the input signal is passed through the chip and not reclocked. Muting does not effect bypassed signal. 106 DDI_VTT Analog Input Bias Input. Selectable input for interfacing standard ECL outputs requiring 50 Ω pull down to V TT power supply for a seamless interface. See Typical Application Circuit for recommended circuit application. 108, 109 DDI, DDI Differential ECL/PECL Input Digital Data Input Signals. Digital input signals from a GS1504 Equalizer or HD crosspoint switch. Because of on chip 50 Ω termination resistors, a PCB trace characteristic impedance of 50 Ω is recommended. 110 PD_VCC Power Positive Supply. Phase detector most positive power supply connection. 112 PDSUB_VEE Power Input Substrate Connection. Connect to phase detector’s most negative power supply. 113 PD_VEE Power Input Negative Supply. Phase detector most negative power supply connection. PIN DESCRIPTIONS (Continued) NUMBER SYMBOL LEVEL TYPE DESCRIPTION |
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Ähnliche Beschreibung - GS1540 |
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