Datenblatt-Suchmaschine für elektronische Bauteile |
|
FM25CL64B-DGTR Datenblatt(PDF) 7 Page - Ramtron International Corporation |
|
FM25CL64B-DGTR Datenblatt(HTML) 7 Page - Ramtron International Corporation |
7 / 14 page FM25CL64B - 64Kb 3V SPI F-RAM Rev. 1.2 Feb. 2011 Page 7 of 14 The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /WP pin. When WPEN is low, the /WP pin is ignored. When WPEN is high, the /WP pin controls write access to the Status Register. Thus the Status Register is write protected if WPEN=1 and /WP=0. This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions. Table 4. Write Protection WEL WPEN /WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected Memory Operation The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike SPI-bus EEPROMs, the FM25CL64B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory begin with a WREN op- code with /CS being asserted and deasserted. The next op-code is WRITE. The WRITE op-code is followed by a two-byte address value. The upper 3- bits of the address are ignored. In total, the 13-bits specify the address of the first data byte of the write operation. This is the starting address of the first data byte of the write operation. Subsequent bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps /CS low. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. The rising edge of /CS terminates a WRITE operation. A write operation is shown in Figure 9. EEPROMs use page buffers to increase their write throughput. This compensates for the technology’s inherently slow write operations. F-RAM memories do not have page buffers because each byte is written to the F-RAM array immediately after it is clocked in (after the 8th clock). This allows any number of bytes to be written without page buffer delays. Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. Following the READ command is a two-byte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first byte of the read operation. This is the starting address of the first byte of the read operation. After the op-code and address are issued, the device drives out the read data on the next 8 clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and /CS is low. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ operation. A read operation is shown in Figure 10. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. |
Ähnliche Teilenummer - FM25CL64B-DGTR |
|
Ähnliche Beschreibung - FM25CL64B-DGTR |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |