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LA72710V Datenblatt(PDF) 8 Page - Sanyo Semicon Device |
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LA72710V Datenblatt(HTML) 8 Page - Sanyo Semicon Device |
8 / 10 page LA72710V No.A0237-8/10 I 2C Timing Specifications Parameter Symbol min max unit LOW level input voltage VIL -0.5 1.5 V HIGH level input voltage VIH 3.0 5.5 V LOW level output current IOL 3.0 mA SCL clock frequency fSCL 0 100 kHz Set-up time for a repeated START condition tSU:STA 4.7 µs Hold time START condition. After this period, the first clock pulse is generated tHD:STA 4.0 µs LOW period of the SCL clock tLOW 4.7 µs Rise time of both SDA and SDL signals tR 0 1.0 µs HIGH period of the SCL clock tHIGH 4.0 µs Fall time of both SDA and SDL signals tF 0 1.0 µs Data hold time tHD:DAT 0 µs Data set-up time tSU:DAT 250 ns Set-up time for STOP condition tSU:STO 4.0 µs BUS free time between a STOP and START condition tBUF 4.7 µs I 2C Control Conditions Grp-1 (SLAVE ADDRESS 80H) D8 D7 D6 D5 D4 D3 D2 D1 Condition 0 0 Bilingual * 0 1 Main 1 0 Sub 1 1 (Prohibit) * 0 Normal 1 Forced MONO * 0 Normal (MUTE Off) 1 MUTE * 0 ALC Off (Through) 1 ALC On * 0 JUST CLOCK Off 1 JUST CLOCK On * 0 SIF Mode 1 BASE BAND Mode * 0 Fix 1 Prohibit (TEST Mode) *:Initial condition Read out data D8 D7 D6 D5 D4 D3 D2 D1 Condition 0 0 0 0 0 0 Fixed 0 Normal 1 Bilingual det 0 Normal 1 Stereo det |
Ähnliche Teilenummer - LA72710V |
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Ähnliche Beschreibung - LA72710V |
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