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LB1991V Datenblatt(PDF) 2 Page - Sanyo Semicon Device |
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LB1991V Datenblatt(HTML) 2 Page - Sanyo Semicon Device |
2 / 7 page LB1991V No.5792-2/7 Electrical Characteristics at Ta = 25°C, VCC1 = 3V, VCC2 = 4.75V, VS = 1.5V Ratings Parameter Symbol Conditions min typ max Unit Supply Current VCC1 current drain ICC1 IOUT = 100mA 3 5 mA VCC2 current drain ICC2 IOUT = 100mA 7.0 10.0 mA VCC1 quiescent current ICC1Q VSTBY = 0V 1.5 3.0 mA VCC2 quiescent current ICC2Q VSTBY = 0V 100 µA VS quiescent current ISQ VSTBY = 0V 75 100 µA VX1 High side residual voltage VXH1 IOUT = 0.2A 0.15 0.22 0.29 V Low side residual voltage VXL1 IOUT = 0.2A 0.15 0.20 0.25 V VX2 High side residual voltage VXH2 IOUT = 0.5A 0.25 0.40 V Low side residual voltage VXL2 IOUT = 0.5A 0.25 0.40 V Output saturation voltage VO(sat) IOUT = 0.8A, Sink + Source 1.4 V Overlap O.L RL = 39Ω × 3, Rangle = 20kΩ *2 72 80 87 % High/low overlap difference ∆O.L (Average upper side overlap) – (Average lower side overlap) *2 -8 +8 % Hall Amplifiers Input offset voltage VHOFF Design target *1 -5 +5 mV Common-mode input voltage range VHCM Rangle = 20k Ω 0.95 2.1 V I/O voltage gain VGVH Rangle = 20k Ω 25.5 28.5 31.5 dB Standby Pin High-level voltage VSTH 2.5 V Low-level voltage VSTL 0.4 V Input current ISTIN VSTBY = 3V 25 40 µA Leakage current ISTLK VSTBY = 0V -30 µA FRC Pin High-level voltage VFRCH 2.5 V Low-level voltage VFRCL 0.4 V Input current IFRCIN VFRC = 3V 25 30 µA Leakage current IFRCLK VFRC = 0V -30 µA VH Hall supply voltage VHALL IH = 5mA, VH(+) − VH(−) 0.85 0.95 1.05 V ( −) pin voltage VH(−) IH = 5mA 0.81 0.88 0.95 V FG Comparator Input offset voltage VFGOFF -3 +3 mV Input bias voltage IbFG VFGIN+ = VFGIN− = 1.5V 500 nA Input bias current offset ∆IbFG VFGIN+ = VFGIN− = 1.5V -100 +100 nA Common-mode input voltage range VFGCM 1.2 2.5 V Output high-level voltage VFGOH At the internal pull-up resistors 2.8 V Output low-level voltage VFGOL At the internal pull-up resistors 0.2 V Voltage gain VGFG Design target *1 100 dB Output current (sink) IFGOS For the output pin low level 5 mA Thermal shutdown Operating temperature TSD Design target *1 180 °C Temperature hysteresis ∆TSD Design target *1 20 °C *1: Design target values in the conditions column are not tested. *2: The standard for overlap is the value as measured. |
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Ähnliche Beschreibung - LB1991V |
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