MCM6246

3

MOTOROLA FAST SRAM

Parameter

Symbol

Typ

Max

Unit

Input Capacitance

All Inputs Except Clocks and DQs

E, G, W

Cin

Cck

4

5

6

8

pF

Input/Output Capacitance

DQ

CI/O

5

8

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . .

Output Load

See Figure 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCM6246–17

MCM6246–20

MCM6246–25

MCM6246–35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

17

—

20

—

25

—

35

—

ns

2, 3

Address Access Time

tAVQV

—

17

—

20

—

25

—

35

ns

Enable Access Time

tELQV

—

17

—

20

—

25

—

35

ns

4

Output Enable Access Time

tGLQV

—

6

—

6

—

8

—

10

ns

Output Hold from Address

Change

tAXQX

5

—

5

—

5

—

5

—

ns

Enable Low to Output Active

tELQX

5

—

5

—

5

—

5

—

ns

5, 6, 7

Output Enable Low to Output

Active

tGLQX

0

—

0

—

0

—

0

—

ns

5, 6, 7

Enable High to Output High–Z

tEHQZ

—

8

—

8

—

10

—

12

ns

5, 6, 7

Output Enable High to Output

High–Z

tGHQZ

—

8

—

8

—

10

—

12

ns

5, 6, 7

Power Up Time

tELICCH

0

—

0

—

0

—

0

—

ns

Power Down Time

tEHICCL

—

17

—

20

—

25

—

35

ns

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-

tion conditions during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E going low/E going high.

5. At any given voltage and temperature, tEHQZ max t tELQX min, and tGHQZ max t tGLQX min, both for a given device and from device

to device.

6. Transition is measured

± 500 mV from steady–state voltage.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E

≤ VIL, G ≤ VIL).

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

Figure 1. AC Test Load