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MCM6249WJ25 Datenblatt(PDF) 3 Page - Motorola, Inc

Teilenummer MCM6249WJ25
Bauteilbeschribung  1M x4 Bit Static Random Access Memory
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Hersteller  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCM6249WJ25 Datenblatt(HTML) 3 Page - Motorola, Inc

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MCM6249
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
Cin
Cck
4
5
6
8
pF
Input/Output Capacitance
DQ
CI/O
5
8
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . .
Output Load
See Figure 1a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Note 1)
MCM6249–20
MCM6249–25
MCM6249–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
20
25
35
ns
2, 3
Address Access Time
tAVQV
20
25
35
ns
Enable Access Time
tELQV
20
25
35
ns
4
Output Enable Access Time
tGLQV
6
8
10
ns
Output Hold from Address Change
tAXQX
5
5
5
ns
Enable Low to Output Active
tELQX
5
5
5
ns
5, 6, 7
Output Enable Low to Output Active
tGLQX
0
0
0
ns
5, 6, 7
Enable High to Output High–Z
tEHQZ
0
9
0
10
0
12
ns
5, 6, 7
Output Enable High to Output High–Z
tGHQZ
0
9
0
10
0
12
ns
5, 6, 7
Power Up Time
tELICCH
0
0
0
ns
Power Down Time
tEHICCL
20
25
35
ns
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low/E going high.
5. At any given voltage and temperature, tEHQZ max t tELQX min, and tGHQZ max t tGLQX min, both for a given device and from device
to device.
6. Transition is measured
± 500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤ VIL, G ≤ VIL).
(a)
(b)
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input re-
quirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
TIMING LIMITS
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
480
Figure 1. AC Test Loads


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