MCM62Y308

3

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

SOJ Pin Locations

Symbol

Type

Description

11

K

Input

CLOCK – System clock input pin accepting a minimum 8 ns clock high

or clock low pulse at a minimum 20 ns clock cycle. All other

synchronous inputs excluding the test access port are captured on the

rising edge of this signal.

12

WE

Input

WRITE ENABLE – Write enable is captured on K leading edge. When

asserted this causes the input data D0 – D7 to be written into the RAM

address controlled by the write address counter and increments the

counter for the next write.

21

RE

Input

READ ENABLE – Read enable is captured on K leading edge. When

asserted increments the counter for the next read operation. This

causes a RAM read access from address controlled by the read

address counter to be inserted in the output register Q0 – Q7.

13

WR

Input

WRITE RELOAD – Write reload is captured on K leading edge. When

asserted this causes the write address counter to be initialized to the

contents of the write reload register or “cleared” as specified by control

register bit 3. See control register bit 3 for “cleared” description.

20

RR

Input

READ RELOAD – Read reload is captured on K leading edge. When

asserted this causes the read address counter to be initialized to the

contents of the read reload register or “cleared” as specified by control

register bit 5. See control register bit 5 for “cleared” description.

22

G

Input

OUTPUT ENABLE – When asserted low causes the outputs Q0 – Q7

to become active and when deasserted high causes them to High–Z.

This pin can be either synchronous with K leading edge or

asynchronous as specified by control register bit 7.

9, 8, 7, 6, 5, 4, 3, 2

D0 – D7

Input

DATA INPUT – The levels on these pins are captured on the K leading

edge. The value captured will be written into the RAM if WE is also

asserted and the expand ID bits match the upper three bits of the write

address counter.

24, 25, 26, 27, 28, 29, 30, 31

Q0 – Q7

Output

DATA OUTPUT – Data outputs are available from the read output

register < 15 ns from the rising edge of K when RE or RR is asserted.

outputs are disabled when the upper three bits of the read address

counter do not match the three expand ID bits of the control register.

G will also control the disabling of the outputs either synchronously or

asynchronously. See G description.

17, 32

RRF, WRF

Output

ROLL–OVER FLAG – These signals are asserted high on the clock

cycle where the address counters (write address counter for WRF and

read address counter for RRF) roll–over to 0000 during count down.

During count up these pins must be treated as don’t cares.

16, 1

RRR, WRR

Input

ROLL–OVER RESET – The level on these pins is captured on the K

leading edge. When asserted low, each will reset their associated

roll–over flag output.

TEST ACCESS PORT PIN DESCRIPTIONS (The Test Access Port Conforms with the IEEE Standard 1149.1. It is also Used

to Load Device Specific Registers Used to Configure the MCM62Y308.)

SOJ Pin Locations

Symbol

Type

Description

15

TCK

Input

TEST CLOCK – Samples and clocks all TAP events. All inputs are

captured on TCK rising edge and all outputs propagate from TCK falling

edge. It also can take the place of K in device operation in certain test

conditions.

18

TMS

Input

TEST MODE SELECT – Sampled on the rising edge of TCK.

Determines the movement through the TAP state machine (Figure 2).

This circuit is designed in such a way that an undriven input will

produce a response identical to the application of a logic 1.

14

TDI

Input

TEST DATA IN – Sampled on the rising edge of TCK. This is the input

side of the serial register placed between TDI and TDO. The register

placed between TDI and TDO is determined by the state of the TAP

state machine and what instruction is active in the TAP instruction

register. This circuit is designed in such a way that an undriven input

will produce a response identical to the application of a logic 1.

19

TDO

Output

TEST DATA OUT – Output that is active depending on the state of the

TAP state machine. Output changes off the trailing edge of TCK. This is

the output side of the serial register placed between TDI and TDO.