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MCM6341ZP11 Datenblatt(PDF) 8 Page - Motorola, Inc

Teilenummer MCM6341ZP11
Bauteilbeschribung  128K x 24 Bit Static Random Access Memory
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Hersteller  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

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MCM6341
8
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
P
Sb l
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
Ui
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
10
11
12
15
ns
5
Address Setup Time
tAVEL
0
0
0
0
ns
Address Valid to End of Write
tAVEH
9
10
10
12
ns
Address Valid to End of Write (G
High)
tAVEH
8
9
9
10
ns
Enable Pulse Width
tELEH,
tELWH
9
10
10
12
ns
6, 7
Enable Pulse Width (G High)
tELEH,
tELWH
8
9
9
10
ns
6, 7
Data Valid to End of Write
tDVEH
4
5
5
6
ns
Data Hold Time
tEHDX
0
0
0
0
ns
Write Recovery Time
tEHAX
0
0
0
0
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELWH
tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)


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