MCM64PC32T

•MCM64PC64T

9

MOTOROLA FAST SRAM

MCM64PC32T–66

MCM64PC32T–66

Parameter

Symbol

Min

Max

Unit

Notes

Cycle Time

tKHKH

15

—

ns

Clock Access Time

tKHQV

—

8

ns

5

Output Enable to Output Valid

tGLQV

—

6

ns

5

Clock High to Output Active

tKHQX1

0

—

ns

5, 7

Clock High to Output Change

tKHQX2

2

—

ns

5, 7

Output Enable to Output Active

tGLQX

0

—

ns

5, 7

Output Disable to Q High–Z

tGHQZ

—

8

ns

6, 7

Clock High to Q High–Z

tKHQZ

2

8

ns

6, 7

Clock High Pulse Width

tKHKL

5

—

ns

Clock Low Pulse Width

tKLKH

5

—

ns

Setup Times:

Address

Address Status

Data In

Write

Address Advance

Chip Enable

tAVKH

tADSVKH

tDVKH

tWVKH

tADVVKH

tEVKH

2.5

—

ns

4

Hold Times:

Address

Address Status

Data In

Write

Address Advance

Chip Enable

tKHAX

tKHADSX

tKHDX

tKHWX

tKHADVX

tKHEX

0.5

—

ns

4

NOTES:

1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.

2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.

3. All read and write cycle timings are referenced from K or G.

4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

5. Tested per AC Test Load.

6. Measured at

7. This parameter is sampled and is not 100% tested.