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DAC2932PFBRG4 Datenblatt(PDF) 6 Page - Texas Instruments

Teilenummer DAC2932PFBRG4
Bauteilbeschribung  Dual, 12-Bit, 40MSPS Digital-to-analog Converter
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC2932PFBRG4 Datenblatt(HTML) 6 Page - Texas Instruments

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DAC2932
SBAS279D − AUGUST 2003 − REVISED JULY 2005
www.ti.com
6
TIMING INFORMATION
tCP
tCL
tDO2
tDO1
tS1
tS2
tH1
tH2
tCH
DAC1 (n
− 1)
CLK
I−DAC OUT1
I−DAC OUT2
DAC2 (n
− 1)
DAC2 (n)
DAC2 (n + 1)
DAC1 (n)
DAC1 (n +1)
(n
− 2)
(n
− 2)
(n
− 1)
(n
− 1)
(n)
(n)
Data In
[D11:D0]
Figure 1. Timing Diagram of I-DAC
TIMING REQUIREMENTS(1,2): I-DAC
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
tCP
Clock cycle time (period)
25
ns
tCL
Clock low time
10
ns
tCH
Clock high time
10
ns
tS1
Data setup time, I-DAC1
1
5
ns
tS2
Data setup time, I-DAC2
1
5
ns
tH1
Data hold time, I-DAC1
3.35
5
ns
tH2
Data hold time, I-DAC2
3.35
5
ns
tDO1(3)
Output delay time, I-DAC1
tS1 + tCP
ns
tDO2(3)
Output delay time, I-DAC2
tS2+(tCP/2)
ns
CS hold time (pulse width)
2.49
ns
CS to clock rising or falling edge setup time
0.52
ns
STBY rise time to IOUT
17
μs
PD fall time to IOUT (I-DAC coming out of power-down mode)
22
μs
(1) Based on design simulation and characterization; not production tested.
(2) All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.
(3) Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.


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