74AC11643

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS057A − JULY 1987 − REVISED APRIL 1993

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

High-Density 24-Pin Packages

Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

125

°C

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

These octal bus transceivers are designed for asynchronous communication between data buses. These

devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at

the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the

buses are effectively isolated.

The 74AC11643 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OPERATION

OE

DIR

OPERATION

L

L

B data to A bus

L

HA data to B bus

H

X

Isolation

logic diagram (positive logic)

1

2

A1

B1

3 EN1 [BA]

24

DIR

3 EN2 [AB]

1

A1

2

A2

B1

23

3

A3

4

A4

9

A5

10

A6

11

A7

12

A8

B2

22

B3

21

B5

17

B4

20

B6

16

B8

14

B7

15

OE

1

13

24

23

1

G3

13

OE

DIR

1

To 7 Other Channels

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

DW OR NT PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

DIR

B1

B2

B3

B4

B5

B6

B7

B8

OE

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.