ADS8555

SBAS531B

– DECEMBER 2010 – REVISED FEBRUARY 2011

www.ti.com

PIN DESCRIPTIONS (continued)

DESCRIPTION

NAME

PIN #

PARALLEL INTERFACE (PAR/SER = 0)

SERIAL INTERFACE (PAR/SER = 1)

Word mode (WORD/BYTE = 0):

Select SDO_A input.

Data bit 0 (LSB) input/output

DB0/SEL_A

17

DIO/DI

When high, SDO_A is active. When low, SDO_A is disabled.

Byte mode (WORD/BYTE = 1):

Should always be high.

Connect to BGND or BVDD

When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been

started and remains high during the entire process. Transitions low when the conversion data of all six channels

are latched to the output register and remains low thereafter.

In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started

BUSY/INT

18

DO

When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion has been

completed and goes low with the first read data access.

The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register.

Chip select input.

Frame synchronization.

CS/FS

19

DI/DI

When low, the parallel interface is enabled. When

The falling edge of FS controls the frame transfer.

high, the interface is disabled.

Read data input.

RD

20

DI

When low, the parallel data output is enabled.

Connect to BGND

When high, the data output is disabled.

Hardware mode (HW/SW = 0): Conversion start of channel pair C.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].

CONVST_C

21

DI

Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only;

connect to BGND or BVDD otherwise

Hardware mode (HW/SW = 0): Conversion start of channel pair B.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].

CONVST_B

22

DI

Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only;

connect to BGND or BVDD otherwise

Hardware mode (HW/SW = 0): Conversion start of channel pair A.

The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].

CONVST_A

23

DI

Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode

(CR bit C23 = 1): Conversion start of channel pair A only

Standby mode input. When low, the entire device is powered down (including the internal clock and reference).

STBY

24

DI

When high, the device operates in normal mode.

25, 32,

37, 38,

Analog ground, connect to analog ground plane

43, 44,

AGND

P

Pin 25 may have a dedicated ground if the difference between its potential and AGND is always kept within

49, 52,

±300mV.

53, 55,

57, 59

26, 34,

Analog power supply (4.5V to 5.5V). Decouple each pin with a 100nF ceramic capacitor to AGND. Use an

35, 40,

additional 10

μF capacitor to AGND close to the device but without compromising the placement of the smaller

AVDD

41, 46,

P

capacitor. Pin 26 may have a dedicated power supply if the difference between its potential and AVDD is always

47, 50,

kept within

±300mV.

60

Hardware mode (HW/SW = 0): Input voltage range select input.

When low, the analog input range is

RANGE/XCLK

27

DI/DIO

Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal

conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND.

Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The

RESET

28

DI

RESET pulse should be at least 50ns long.

Output mode selection input.

When low, data are transferred in word mode using

DB[15:0]. When high, data are transferred in byte

WORD/BYTE

29

DI

Connect to BGND

mode using DB[15:8] with the byte order controlled

complete 16-bit transfer.

Negative supply voltage for the analog inputs (

–16.5V to –5V).

HVSS

30

P

Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10

μF capacitor to AGND close

to the device but without compromising the placement of the smaller capacitor.

Positive supply voltage for the analog inputs (5V to 16.5V). Decouple with a 100nF ceramic capacitor to AGND

HVDD

31

P

placed next to the device and a 10

μF capacitor to AGND close to the device but without compromising the

placement of the smaller capacitor.

Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26

CH_A0

33

AI

(RANGE_A) in software mode.

Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26

CH_A1

36

AI

(RANGE_A) in software mode.

8

© 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): ADS8555