Datenblatt-Suchmaschine für elektronische Bauteile |
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CDCE949-Q1 Datenblatt(PDF) 5 Page - Texas Instruments |
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CDCE949-Q1 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 32 page CDCE949-Q1 www.ti.com SCAS891 – FEBRUARY 2010 RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1) MIN NOM MAX UNIT fXtal Crystal Input frequency range (fundamental mode) 8 27 32 MHz ESR Effective series resistance 100 Ω fPR Pulling range (0 V ≤ VCtrl ≤ 1.8 V) (2) ±120 ±150 ppm V(Ctrl) Frequency control voltage 0 VDD V C0/C1 Pullability ratio 220 CL On-chip load capacitance at Xin and Xout 0 20 pF (1) For more information about VCXO configuration and crystal recommendation see application report SCAA085. (2) Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm applies for crystal listed in the application report SCAA085. EEPROM SPECIFICATION MIN TYP MAX UNIT EEcyc EEcyc programming cycles of EEPROM 1000 cycles EEret EEret data retention 10 years CLK_IN TIMING REQUIREMENTS over recommended ranges of supply voltage, load and operating free-air temperature MIN NOM MAX UNIT PLL Bypass Mode 0 160 f(CLK) LVCMOS clock input frequency MHz PLL Mode 8 160 tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns dutyCLK Duty cycle CLK at VDD / 2 40% 60% SDA/SCL TIMING REQUIREMENTS see Figure 11 STANDARD FAST MODE MODE UNIT MIN MAX MIN MAX f(SCL) SCL clock frequency 0 100 0 400 kHz tsu(START) START setup time (SCL high before SDA low) 4.7 0.6 ms th(START) START hold time (SCL low after SDA low) 4 0.6 ms tw(SCLL) SCL low-pulse duration 4.7 1.3 ms tw(SCLH) SCL high-pulse duration 4 0.6 ms th(SDA) SDA hold time (SDA valid after SCL low) 0 3.45 0 0.9 ms tsu(SDA) SDA setup time 250 100 ns tr SCL/SDA input rise time 1000 300 ns tf SCL/SDA input fall time 300 300 ns tsu(STOP) STOP setup time 4.0 0.6 ms tBUF Bus free time between a STOP and START condition 4.7 1.3 ms Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCE949-Q1 |
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