CDCEL937QPWRQ1 datasheet(5/30 Pages) TI1

Teilenummer	CDCEL937QPWRQ1

Bauteilbeschribung	PROGRAMMABLE 3-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V, AND 3.3-V LVCMOS OUTPUTS

Download	30 Pages

Scroll/Zoom	100%

Hersteller	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

Logo

5 / 30 page

CDCE937-Q1

CDCEL937-Q1

www.ti.com

SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS

(1)

MIN

NOM

MAX

UNIT

fXtal

Crystal input frequency range (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

fPR

Pulling range (0 V

≤ Vctrl ≤ 1.8 V)(2)

±120

±150

ppm

Frequency control voltage, Vctrl

0

VDD

V

C0/C1

Pullability ratio

220

CL

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm

applies for crystal listed in the application report (SCAA085).

EEPROM SPECIFICATION

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

1000

cycles

EEret

Data retention

10

years

CLK_IN TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating ambient temperature

MIN

NOM

MAX

UNIT

PLL bypass mode

0

160

fCLK

LVCMOS clock input frequency

MHz

PLL mode

8

160

tr / tf

Rise and fall time CLK signal (20% to 80%)

3

ns

dutyCLK

Duty cycle CLK at VDD/2

40%

60%

SDA/SCL TIMING REQUIREMENTS

see Figure 12

STANDARD

FAST

MODE

UNIT

MIN

MAX

MIN

MAX

fSCL

SCL clock frequency

0

100

0

400

kHz

tsu(START)

START setup time (SCL high before SDA low)

4.7

0.6

ms

th(START)

START hold time (SCL low after SDA low)

4

0.6

ms

tw(SCLL)

SCL low-pulse duration

4.7

1.3

ms

tw(SCLH)

SCL high-pulse duration

4

0.6

ms

th(SDA)

SDA hold time (SDA valid after SCL low)

0

3.45

0

0.9

ms

tsu(SDA)

SDA setup time

250

100

ns

tr

SCL/SDA input rise time

1000

300

ns

tf

SCL/SDA input fall time

300

ns

tsu(STOP)

STOP setup time

4

0.6

ms

tBUS

Bus free time between a STOP and START condition

4.7

1.3

ms

Submit Documentation Feedback

5

Product Folder Link(s): CDCE937-Q1

Ähnliche Beschreibung - CDCEL937QPWRQ1

Hersteller	Teilenummer	Datenblatt	Bauteilbeschribung
Texas Instruments	CDCE937	481Kb / 30P	[Old version datasheet] Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V and 3.3-V LVCMOS Outputs
	CDCE925	485Kb / 27P	[Old version datasheet] PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS
	CDCE949-Q1	717Kb / 32P	[Old version datasheet] PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS
	CDCE913	515Kb / 23P	[Old version datasheet] Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
	CDCE913	376Kb / 21P	[Old version datasheet] Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
	CDCE913	681Kb / 26P	[Old version datasheet] Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
	CDCEL913-Q1	662Kb / 26P	[Old version datasheet] Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
	CDCE913	460Kb / 25P	[Old version datasheet] Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
	CDCE813-Q1_1904	1Mb / 34P	[Old version datasheet] Programmable 1-PLL Clock Synthesizer and Jitter Cle With 2.5-V and 3.3-V Outputs
	CDCE813-Q1	1Mb / 29P	[Old version datasheet] Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs

More results

CDCEL937QPWRQ1 Datenblatt(PDF) 5 Page - Texas Instruments

CDCEL937QPWRQ1 Datenblatt(HTML) 5 Page - Texas Instruments

Ähnliche Teilenummer - CDCEL937QPWRQ1

Ähnliche Beschreibung - CDCEL937QPWRQ1

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datenblatt Download

Link URL