Datenblatt-Suchmaschine für elektronische Bauteile |
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CDCVF2505IDRQ1 Datenblatt(PDF) 2 Page - Texas Instruments |
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CDCVF2505IDRQ1 Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 10 page Edge Detect Typical <10 MHz Power Down 3-State 1 8 3 2 5 7 CLKOUT 1Y0 1Y1 1Y2 1Y3 CLKIN PLL 25 W 25 W 25 W 25 W 25 W CDCVF2505-Q1 SCAS867 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com FUNCTION TABLE INPUT OUTPUTS CLKIN 1Y[0–3] CLKOUT L L L H H H <10 MHz(1) Z Z (1) Below 2 MHz (typical) the device goes into power-down mode, during which the PLL is turned off and the outputs enter into Hi-Z mode. If a >10-MHz signal is applied at CLKIN, the PLL turns on, reacquires lock, and stabilizes after approximately 100 µs. The outputs are then enabled. FUNCTIONAL BLOCK DIAGRAM TERMINAL FUNCTIONS NAME NO. I/O DESCRIPTION 1Y0 3 1Y1 2 Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- Ω series O damping resistor. 1Y2 5 1Y3 7 Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must CLKIN 1 I have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the PLL to phase lock the feedback signal to CLKIN. Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside CLKOUT 8 O the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs. GND 4 Power Ground VDD3.3V 6 Power 3.3-V supply 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF2505-Q1 |
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