CDCP1803-EP

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

EN

1

I

ENABLE: Enables or disables all outputs simultaneously.

(with 60-k

Ω pullup)

EN = 1: outputs on according to S[2:0] settings

EN = 0: outputs Y[2:0] off (high impedance)

See Table 1 for details.

IN, IN

3, 4

I (differential)

Differential input clock. Input stage is sensitive and has a wide common-mode range.

Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,

CML, HSTL). Because the input is high-impedance, it is recommended to terminate the

PCB transmission line before the input (e.g., with 100

Ω across input). Input can also be

driven by a single-ended signal if the complementary input is tied to VBB. A

more-advanced scheme for single-ended signals is given in the Application Information

section near the end of this document.

The inputs employ an ESD structure protecting the inputs in case of an input voltage

exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs

NC

12

No connect. Leave this terminal open or tie to ground.

S[2:0]

24, 19, 18

I

Select mode of operation. Defines the output configuration of Y[2:0], see Table 1 for

(with 60-k

Ω pullup)

configuration.

VBB

6

O

Bias voltage output can be used to bias unused complementary input IN for

single-ended input signals.

is limited to about 1.5 mA.

2, 5

Supply

Supply voltage PECL input + internal logic

8, 11, 14,

Supply

PECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling

17, 20, 23

CAUTION: In this mode, no voltage from outside may be forced, because internal

diodes could be forced in forward direction. Thus, it is recommended to disconnect the

output if it is not being used.

7, 13

Supply

Device ground

Y[2:0]

9, 15, 21

O (LVPECL)

LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided

Y[2:0]

10, 16, 22

copies of clock IN based on selected mode of operation S[2:0]. If an output is unused,

the output can simply be left open to save power and minimize noise impact to the

remaining outputs.

Copyright © 2008, Texas Instruments Incorporated

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