DAC5687-EP datasheet(7/75 Pages) TI1

Teilenummer	DAC5687-EP

Bauteilbeschribung	16-BIT 500-MSPS 2쨈??쨈 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

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ELECTRICAL CHARACTERISTICS

DAC5687-EP

SGLS333 – JUNE 2006

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V,

IOVDD = 3.3 V, DVDD = 1.8 V, IOUT

FS = 19.2 mA (unless otherwise noted)

DC SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

16

Bits

DC ACCURACY(1)

INL

Integral nonlinearity

1 LSB = IOUTFS/216, TMIN to TMAX

±4

LSB

DNL

Differential nonlinearity

±5

LSB

ANALOG OUTPUT

Coarse gain linearity

±0.04

LSB

Worst case error from ideal linearity

Fine gain linearity

±3

LSB

Offset error

Mid code offset

0.01

%FSR

Without internal reference

1

%FSR

Gain error

With internal reference

0.7

%FSR

With internal reference, dual DAC,

Gain mismatch

–2

2

%FSR

and SSB mode

Minimum full-scale output current(2)

2

mA

Maximum full-scale output current(2)

20

mA

AVDD

Output compliance range(3)

IOUTFS = 20 mA

V

– 0.5 V

+ 0.5 V

Output resistance

300

k

Ω

Output capacitance

5

pF

REFERENCE OUTPUT

Reference voltage

1.14

1.2

1.26

V

Reference output current(4)

100

nA

REFERENCE INPUT

VEXTIO

Input voltage range

0.1

1.25

V

Input resistance

1

M

Ω

Small signal bandwidth

1.4

MHz

Input capacitance

100

pF

TEMPERATURE COEFFICIENTS

ppm of

Offset drift

±1

FSR/°C

Without internal reference

±15

ppm of

Gain drift

FSR/°C

With internal reference

±30

ppm of

Reference voltage drift

±8

FSR/°C

POWER SUPPLY

AVDD

Analog supply voltage

3

3.3

3.6

V

DVDD

Digital supply voltage

1.71

1.8

2.15

V

CLKVDD

Clock supply voltage

3

3.3

3.6

V

IOVDD

I/O supply voltage

1.71

3.6

V

PLLVDD

PLL supply voltage

3

3.3

3.6

V

(1)

Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25

Ω each to AVDD.

(2)

Nominal full-scale current, IOUTFS , equals 32× the IBIAS current.

(3)

The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5687 device. The upper limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(4)

Use an external buffer amplifier with high impedance input to drive any external load.

7

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