Datenblatt-Suchmaschine für elektronische Bauteile |
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SM320VC33PGEA120EP Datenblatt(PDF) 2 Page - Texas Instruments |
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SM320VC33PGEA120EP Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 62 page SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 description The SM320VC33-EP DSP is a 32-bit, floating-point processor manufactured in 0.18-μm four-level-metal CMOS (TImeline) technology. The SM320VC33-EP is part of the SM320C3x™ generation of DSPs from Texas Instruments. The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM320VC33-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The SM320VC33-EP can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. JTAG scan-based emulation logic The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. The Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back tests to be performed through that JTAG domain. The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of multiple processors conforming to the TI emulation standard. These pins are open collector type outputs which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins. The VC33 instruction register is 8 bits long. Table 1 shows the instruction code. The uses of SAMPLE and HIGHZ opcodes, though defined, have no meaning for the SM320VC33-EP, which has no boundary scan. For example, HIGHZ affects only the dummy cell (no meaning) and does not put the device pins in a high-impedance state. |
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