SN74ACT2440

NuBus

™ INTERFACE CONTROLLER

SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991

POST OFFICE BOX 655303

5

Terminal Functions (continued)

NUBUS

PIN

DESCRIPTION

NAME

NO.

DESCRIPTION

ACK

21

Transfer acknowledge. This bidirectional I/O pin signals the end of a transaction. It also signals attention cycles.

ARB0

11

Arbitration signals. These four I/O lines are bused and binary encoded in the same manner as the ID3–ID0 lines. During an

ARB0

ARB1

13

Arbitration signals. These four I/O lines are bused and binary encoded in the same manner as the ID3 ID0 lines. During an

arbitration contest, contending modules compare these lines with the binary value of their own ID3–ID0 lines. Each module

ARB2

15

,g

y

drives the ARB3–ARB0 lines according to the rules of the distributed arbitration logic. The net effect of the arbitration contest

T

ARB3

17

is that the ARB3–ARB0 lines carry the binary-encoded number of the next NuBusT

™ owner.

CLK

26

Clock. The NuBus

™ Clock signal is tied directly to the controller. Bus arbitration and data transfers are synchronized to this

signal.

ID0

30

Card-slot identification. These four input lines are not bused but are binary encoded at each card-slot position to specify

ID0

ID1

29

yy

the module’s position on the backplane. The controller uses these inputs when requesting access to the NuBus

™.

ID2

28

g

ID3

27

NMRQ

25

NonMaster request. This asynchronous output on the ’ACT2440 is controlled by the NMRQ input on the ’ACT2440 and can

be used in applications where the local board is not capable becoming a bus master but wishes to issue an interruptIn

be used in a

lications where the local board is not ca able becoming a bus master but wishes to issue an interru t. In

systems that use the NMRQ line as a bused signal (all NMRQ signals tied common), the NMRQ output on the ’ACT2440

t fi t b b ff

d th

h

ll

t

d i

I

t

th t

th NMRQ i

l

idi id

l it

t li

must first be buffered through an open-collector driver. In systems that use the NMRQ signal as an individual interrupt line,

the NMRQ output on the ’ACT2440 does not have to be buffered with an open-collector driver.

RESET

10

Reset. This asynchronous input monitors the NuBus

™ RESET line. When taken active (low), it intializes the NuBus™

controller.

RQST

23

Bus request. This bidirectional I/O pin is asserted by the controller when the local board wants ownership of the bus.

SPV

6

System parity valid. System parity valid signals as the NuBus

™ when parity has been generated for the AD31–AD0 lines.The

controller drives this line inactive during master and slave cycles to indicate that no parity has been generated.

START

20

Start. This bidirectional I/O pin is asserted at the start of a NuBus

™ transaction and also initiates an arbitration contest.

When asserted in conjuction with the ACK line, it denotes special nontransaction cycles called attention cycles.

TM0

7

Transfer mode. At the beginning of a transaction, these two lines indicate the type of transaction being initiated. Later in the

TM1

8

transaction, the responding module uses them to indicate success or failure of the requested transaction.

BYTE DECODE SIGNALS

PIN

DESCRIPTION

NAME

NO.

DESCRIPTION

A0

A1

59

60

Inverted NuBus

™ address inputs. These two controller inputs require inverted versions of the NuBus™ Address signals AD0

and AD1 (as provided from the ’BCT2420 data/address interface device ) These signals in conjuction with the NuBus

™

A1

60

and AD1 (as provided from the ’BCT2420 data/address interface device.) These signals, in conjuction with the NuBus

™

transfer-mode signals (TM0,TM1), define the type of transfer cycle (i.e., byte, halfword, or block).

BT0

61

Byte control outputs. These active-low outputs are decoded from the A0, A1, and TM0 controller inputs. The NuBus

™ signal

BT0

BT1

62

Byte control out uts. These active low out uts are decoded from the A0, A1, and TM0 controller in uts. The NuBus

signal

TM1 defines whether the current cycle is a read or write. Refer to Table 1, for additional details

BT2

63

y,

BT3

64