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SN74AUP2G02 Datenblatt(PDF) 2 Page - Texas Instruments

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Teilenummer SN74AUP2G02
Bauteilbeschribung  LOW-POWER DUAL 2-INPUT POSITIVE-NOR GATE
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

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SN74AUP2G02
SCES753C – SEPTEMBER 2009 – REVISED MAY 2010
www.ti.com
The SN74AUP2G02 performs the Boolean function Y = A + B or Y = A × B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP2G02YFPR
_ _ _ H B _
0.23-mm Large Bump – YFP (Pb-free)
uQFN – DQE
Reel of 5000
SN74AUP2G02DQER
PP
–40°C to 85°C
QFN – RSE
Reel of 5000
SN74AUP2G02RSER
PP
SSOP – DCU
Reel of 3000
SN74AUP2G02DCUR
H02_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
B
H
X
L
X
H
L
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
Pin number shown are for DCU and DQE packages.
2
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP2G02


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