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TSB41BA3BTPFPEP Datenblatt(PDF) 4 Page - Texas Instruments

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Teilenummer TSB41BA3BTPFPEP
Bauteilbeschribung  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER  
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Hersteller  TI1 [Texas Instruments]
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TSB41BA3BEP
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS362—MAY 2006
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description (continued)
When the power supply of the TSB41BA3B-EP is off while the twisted-pair cables are connected, the
TSB41BA3B-EP transmitter and receiver circuitry present a high-impedance signal to the cable that does not
load the device at the other end of the cable.
When the TSB41BA3B-EP is used without one or more of the ports brought out to a connector, the twisted-pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred
method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and
TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be
connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can
be left unconnected. The TPBIAS_SD terminal can be left unconnected.
If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+
and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA–
terminals of an unused port can be left unconnected. The TPBIAS_SD terminal can be left unconnected.
If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be
left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination
network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS_SD terminal
must be pulled to ground through a 1.2-k
Ω or less resistor.
To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0,
S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-k
Ω resistor. The port must be operated
in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the
port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly
to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only
mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode
is provided to ensure that 1394b signaling is never sent across a 1394a cable.
NOTE:
A bilingual port can only connect to a 1394b-only port that operates at S400b. It can not establish
a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to
a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b
can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only
connect to a 1394b-only port at S100b.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals
must be tied to ground through a 1-k
Ω resistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the
self-ID packet. They can be pulled high through a 1-k
Ω resistor or hardwired low as a function of the equipment
design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default
power class status for the node (the need for power from the cable or the ability to supply power to the cable);
see Table 1. The contender bit in the PHY register set indicates that the node is a contender either for the
isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3B-EP, this bit can only
be set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must
set this bit in the PHY register set.
The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node.
The LPS signal from the LLC is used with the LCtrl bit (see Table 2 and Table 3 in the application information
section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the
PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the
state of the LCtrl bit).


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TSB41BA3BTPFPEP TI1-TSB41BA3BTPFPEP Datasheet
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