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CDCLVC1310RHBR Datenblatt(PDF) 8 Page - Texas Instruments |
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CDCLVC1310RHBR Datenblatt(HTML) 8 Page - Texas Instruments |
8 / 28 page CDCLVC1310 SCAS917B – JULY 2011 – REVISED FEBRUARY 2012 www.ti.com LVCMOS OUTPUT CHARACTERISTICS over recommended ranges of supply voltage (VDDO ≤ VDD), load (50 Ω to VDDO/2), and ambient temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT 200 MHz VDDO = 3.135 V 2.5 VDDO = 2.375 V 1.8 VOH Output high voltage V VDDO = 1.6 V 1.15 VDDO = 1.35 V 0.95 VDDO = 3.135 V 0.5 VDDO = 2.375 V 0.4 VOL Output low voltage V VDDO = 1.6 V 0.4 VDDO = 1.35 V 0.4 VDDO = 3.3 V 15 VDDO = 2.5 V 20 ROUT Output impedance Ω VDDO = 1.8 V 25 VDDO = 1.5 V 30 tSLEW-RATE Output rise/fall slew rate 20% to 80% 5 V/ns tSK Output skew 30 50 ps tSK,PP Part-to-part skew(1) 2 ns tDELAY Propagation delay 2 ns Single-ended input, VDD = 3.3 V, 25 VDDO = 3.3 V Single-ended input, VDD = 2.5 V/3.3 V, VDDO = 1.5 V/1.8 V/2.5 V, fIN/OUT 30 = 125 MHz tRJIT System-level additive jitter(2) fS, RMS Differential input, VDD = 3.3 V, 30 VDDO = 3.3 V Differential input, VDD = 2.5V/3.3V, VDDO = 1.5V/1.8V/2.5V, fIN/OUT = 30 125 MHz 10-kHz offset(3) –145 100-kHz offset(3) –156 1-MHz offset(3) –163 10-MHz offset(3) –164 20-MHz offset(3) –164 NF Noise floor dBc/Hz 10-kHz offset(4) –145 100-kHz offset(4) –155 1-MHz offset(4) –160 10-MHz offset(4) –161 20-MHz offset(4) –162 odc Output duty cycle fIN/OUT = 125 MHz, idc = 50% (5) 45% 55% tEN Output enable/disable time 2 Cycle MUXISOLAT MUX isolation(6) 125 MHz 55 dB ION (1) Part-to-part skew is calculated as the difference between the fastest and the slowest tpd across multiple devices. (2) Integration range: 12 kHz –20 MHz; input source see Application Information (3) Single-ended input, fIN/OUT = 125 MHz, VDD = VDDO = 3.3 V (4) Differential input, fIN/OUT = 125 MHz, VDD = VDDO = 3.3 V (5) Stable VIH, VIL, and VCM (6) See Figure 18. 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): CDCLVC1310 |
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