Datenblatt-Suchmaschine für elektronische Bauteile |
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UC1875-SP Datenblatt(PDF) 8 Page - Texas Instruments |
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UC1875-SP Datenblatt(HTML) 8 Page - Texas Instruments |
8 / 20 page UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com SOFTSTART:(soft start): SOFTSTART will remain at GND as long as VIN is below the UVLO threshold. SOFTSTART will be pulled up to about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current-fault (CS+ voltage exceeding 2.5 V), SOFTSTART will be pulled to GND and them ramp to 4.8 V. If a fault occurs during the SOFTSTART cycle, the outputs will be immediately disabled and SOFTSTART must charge fully prior to resetting the fault latch. For paralleled controllers, the SOFTSTART pins may be paralled to a single capacitor, but the charge currents will be additive. VC (Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWRGND pin with low ESR, low ESL capacitors VIN (Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should by bypassed directly to the GND pin with low ESR, low ESL capacitors. NOTE When VIN exceeds the UVLO threshold the supply current (IIN) will jump from about 100 µA to a current in excess of 20 µA. If the UC1875-SP is not connected to a well bypassed supply, it may immediately enter UVLO again. VREF: This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled while VIN is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR, low ESL, capacitor to the GND pin. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP |
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Ähnliche Beschreibung - UC1875-SP |
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