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UC2825AQDWRQ1 Datenblatt(PDF) 8 Page - Texas Instruments

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Teilenummer UC2825AQDWRQ1
Bauteilbeschribung  HIGH-SPEED PWM CONTROLLER
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UVLO, Soft Start, and Fault Management
FAULT
V
SS
PWM
OFF
ON
0.2 V
1.2 V
5.0 V
1.2 V
Active-Low Outputs During UVLO
UDG-95106
UDG-95108
UC2825A-Q1
SLUS781 – SEPTEMBER 2007
Soft start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error
amplifier output is also forced low. While the internal 9-
μA source charges the SS pin, the error amplifier output
follows until closed loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start capacitor is
then discharged by a 250-
μA current sink. No more output pulses are allowed until the soft-start capacitor is fully
discharged and ILIM is below 1.2 V. At this time, the fault latch resets and the chip executes a soft start.
Should the fault latch get set during soft start, the outputs are immediately terminated, but the soft-start capacitor
does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous
fault conditions.
Figure 5. Soft-Start and Fault Waveforms
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to
operate.
Figure 6. Output Voltage vs Output Current
Figure 7. Output Voltage and Current During UVLO
8
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Copyright © 2007, Texas Instruments Incorporated


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