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74HCT259D-Q100 Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74HCT259D-Q100 Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 20 page 74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 30 July 2012 2 of 20 NXP Semiconductors 74HC259-Q100; 74HCT259-Q100 8-bit addressable latch Useful as a 3-to-8 active HIGH decoder Input levels: For 74HC259-Q100: CMOS level For 74HCT259-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC259D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT259D-Q100 74HC259PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT259PW-Q100 74HC259BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm SOT763-1 74HCT259BQ-Q100 Fig 1. Logic symbol Fig 2. IEC logic symbol mna573 D A0 A1 A2 MR LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 14 15 12 11 10 9 7 6 5 4 3 2 1 13 mna572 1 9,10D Z9 G8 G10 C10 8R 13 15 14 0 1 2 3 1 2 0 DX 0 7 2 3 4 5 4 6 7 9 10 11 12 5 6 7 G |
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