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74HCT373-Q100 Datenblatt(PDF) 11 Page - NXP Semiconductors |
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74HCT373-Q100 Datenblatt(HTML) 11 Page - NXP Semiconductors |
11 / 24 page 74HC_HCT373_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 10 August 2012 11 of 24 NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state Tamb = 40 Cto+85 C tpd propagation delay Dn to Qn; see Figure 8 [1] VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns LE to Qn; see Figure 9 VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns VCC = 6.0 V - - 37 ns ten enable time OE to Qn; see Figure 10 [2] VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns tdis disable time OE to Qn; see Figure 10 [3] VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 33 ns tt transition time Qn; see Figure 8 and Figure 9 [4] VCC = 2.0 V - - 75 ns VCC = 4.5 V - - 15 ns VCC = 6.0 V - - 13 ns tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns tsu set-up time Dn to LE; see Figure 11 VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns th hold time Dn to LE; see Figure 11 VCC = 2.0 V 5 - - ns VCC = 4.5 V 5 - - ns VCC = 6.0 V 5 - - ns Table 8. Dynamic characteristics 74HC373-Q100 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit |
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