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SN74BCT657NT Datenblatt(PDF) 1 Page - Texas Instruments |
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SN74BCT657NT Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 10 page 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY DW OR NT PACKAGE (TOP VIEW) SN74BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3STATE OUTPUTS SCBS079B − NOVEMBER 1991 − REVISED APRIL 1994 Copyright 1994, Texas Instruments Incorporated 2−1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • 3-State B Outputs Sink 48 mA or 64 mA and Source 12 mA or 15 mA • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) description The SN74BCT657 contains eight noninverting transceivers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus- oriented applications. The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port from the B port. When the output-enable (OE) input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R low), PARITY is an input. When transmitting (T/R high), the parity-select (ODD/EVEN) input is made high or low as appropriate. The A port is then polled to determine the number of high bits. The PARITY output goes to the logic state determined by the parity-select (ODD/EVEN) input and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity. When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN is low (for even parity) and the number of highs on B port is as follows: − Odd and the PARITY input is high, then ERR will be high signifying no error. − Even and the PARITY input is high, then ERR will be low indicating an error. The SN74BCT657 is characterized for operation from 0 °C to 70°C. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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