SN74ACT7801

1024 × 18 CLOCKED FIRST IN, FIRST OUT MEMORY

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

POST OFFICE BOX 655303

4

functional block diagram

OE

D0 − D17

WRTCLK

WRTEN1

WRTEN2

Q0 − Q17

OR

IR

AF/AE

HF

RDCLK

RDEN1

RDEN2

RESET

DAF

Reset

Logic

Synchronous

Write

Control

Synchronous

Read

Control

Read

Pointer

Write

Pointer

Status

Flag

Logic

Register

1024

× 18 RAM

Location 1

Location 2

Location 1023

Location 1024

functional description

inputs

data in (D0 −D17)

Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0 −D8 also carry the

almost-full/almost-empty offset value (X) on a high-to-low transition of the define almost-full (DAF) input.

reset (RESET)

A reset is accomplished by taking reset (RESET) low and generating a minimum of four read-clock (RDCLK)

and write-clock (WRTCLK) cycles. This ensures that the internal read and write pointers are reset and that the

output-ready flag (OR), the half-full flag (HF), and the input-ready flag (IR) are low; the almost-full/almost-empty

flag (AF/AE) is high. The FIFO must be reset upon power up. With the define almost-full (DAF) input at a low

level, a low pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X),

where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the AF/AE

flag using the default value of X = 256.

write enables (WRTEN1, WRTEN2)

The write enables (WRTEN1, WRTEN2) must be high before the rising edge of write clock (WRTCLK) for a word

to be written into memory. The write enables do not affect the storage of the almost-full/almost-empty offset

value (X).