© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN224C • Rev. 1.0.9

8

Physical Dimensions

NOTES:

A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION

WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.

D. LAND PATTERN PER IPC SM-782.

E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.

F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR

TIE BAR PROTRUSIONS.

G. DRAWING FILENAME: MKT-MLP40Arev3.

6.00

6.00

0.80 MAX

0.10 C

SEATING

PLANE

0.08 C 0.05

0.00

(0.20)

C

0.15 C

0.15 C

PIN #1 IDENT

0.50

4.20

4.00

0.50

0.30

4.20

4.00

0.50

0.10

CA B

0.05

C

0.18-0.30

A

B

6.38MIN

0.20MIN

4.77MIN

4.37MAX

0.28 MAX

0.50TYP

(0.80)

X4

X40

E

(DATUM A)

(DATUM B)

PIN #1 ID

Figure 6. 40-Lead, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which

covers Fairchild products.

Ordering Information

Part Number

Operating

Temperature Range

Eco Status

Package

Packing Method

FIN224CMLX

-30 to +70°C

Green

40-Lead, Molded Leadless Package (MLP),

Quad, JEDEC MO-220, 6mm Square

Tape & Reel