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AD1857JRS Datenblatt(PDF) 10 Page - Analog Devices |
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AD1857JRS Datenblatt(HTML) 10 Page - Analog Devices |
10 / 16 page AD1857/AD1858 REV. 0 –10– OPERATING FEATURES Serial Data Input Port The AD1857/AD1858 use the frequency of the left/ right and master input clocks to determine the input sample rate. Gen- erally, the master clock (MCLK) is divided down to synthesize the left/ right clock (LRCLK). LRCLK must run continuously and transition twice per stereo sample period (except in the left- justified DSP serial port style mode, when it transitions four times per stereo sample period). The bit clock (BCLK) is edge- sensitive and may be used in a gated or burst mode, i.e., a stream of pulses during data transmission followed by periods of inactivity. The bit clock is only used to write the audio data into the serial input port. It is important that the left/ right clock is “clean,” with monotonic rising and falling edge transitions and no excessive overshoot or undershoot that could cause false clock triggering of the AD1857/AD1858. The AD1857/AD1858’s flexible serial data input port accepts data in twos-complement, MSB first format. The left channel data field always precedes the right channel data field. The input data consists of 16, 18 or 20 bits (16 bits only to the AD1858). All digital inputs are specified to TTL logic levels. The input data port is configured by a control pin, MODE, Pin 3. The AD1857 and the AD1858 are identical except for the serial data input port modes offered. The AD1857 offers I 2S-justified and left-justified modes, for 16-, 18- or 20-bit data words. The AD1858 offers right-justified and DSP serial port style mode for 16-bit data words. Note: During the first 30,000 MCLK cycles after coming out of reset, the AD1857/AD1858 synchronizes its internal sequencer counter to the incoming L RCLK. After this period of time, it is assumed that the L RCLK and the internal AD1857/AD1858 output channels could be switched (L to R and R to L). Therefore, if the incoming L RCLK is stopped and then restarted with a different phase, the AD1857/AD1858 should be reset again to synchronize with this new clock. Serial Input Port Modes The AD1857/AD1858 use an input pin to control the mode configuration of the input data port. MODE (Pin 3) programs the input data port mode as follows: Figure 9 shows the AD1857 left-justified mode. L RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L RCLK transition, with no MSB delay. The left-justified mode can be used in the 16-, 18- or 20-bit input mode. MODE (Pin 3) AD1857 Serial Input Port Mode LO Left-Justified (See Figure 9) HI I 2S-Justified (See Figure 10) MODE (Pin 3) AD1858 Serial Input Port Mode LO Right-Justified (See Figure 11) HI Left-Justified DSP Serial Port Style (See Figure 12) Figure 10 shows the AD1857 I 2S-justified mode. L RCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L RCLK transition, but with a single BCLK period delay. The I2S-justified mode can be used in the 16-, 18- or 20-bit input mode. Figure 11 shows the AD1858 the right-justified mode. L RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 16-bit clock periods from an L RCLK transition so that when there are 64 BCLK periods per L RCLK period, the LSB of the data will be right-justified to the next L RCLK transition. LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LRCLK INPUT MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB Figure 9. AD1857 Left-Justified Mode LRCLK INPUT BCLK INPUT SDATA INPUT LEFT CHANNEL RIGHT CHANNEL MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB Figure 10. AD1857 I2S-Justified Mode LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LRCLK INPUT MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB LSB Figure 11. AD1858 Right-Justified Mode |
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Ähnliche Beschreibung - AD1857JRS |
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