Datenblatt-Suchmaschine für elektronische Bauteile |
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ADF41020 Datenblatt(PDF) 4 Page - Analog Devices |
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ADF41020 Datenblatt(HTML) 4 Page - Analog Devices |
4 / 16 page ADF41020 Data Sheet Rev. 0 | Page 4 of 16 Parameter Min Typ Max Unit Test Conditions/Comments NOISE CHARACTERISTICS Normalized Phase Noise Floor4 −221 dBc/Hz PLL loop bandwidth = 500 kHz Normalized 1/f Noise5 −118 dBc/Hz Normalized to 10 kHz offset at 1 GHz Phase Noise Performance6 At VCO output 5.7 GHz −89 dBc/Hz At 1 kHz offset and 2.5 MHz PFD frequency with 20 kHz loop bandwidth 12.5 GHz7 −82 dBc/Hz At 3 kHz offset and 2.5 MHz PFD frequency with 20 kHz loop bandwidth 17.64 GHz −96 dBc/Hz At 100 kHz offset and 90 MHz PFD frequency with 700 kHz loop bandwidth Spurious Signals 5.7 GHz −80/−86 dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency 12.5 GHz7 −98/<−110 dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency 17.64 GHz −109/−113 dBc At 90 MHz/180 MHz and 90 MHz PFD frequency 1 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 2 Guaranteed by design. Sample tested to ensure compliance. 3 T A = 25°C; AVDD = DVDD = VP = 3.0 V; P = 16; fREF IN = 100 MHz; fPFD = 100 MHz; RFIN = 12.8 GHz. 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log fPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 log N. 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 6 The phase noise is measured with a Rohde & Schwarz FSUP spectrum analyzer. The reference is provided by a Rohde & Schwarz SMA100A. 7 The phase noise and spurious noise is measured with the EV-ADF41020EB1Z evaluation board and the Rohde & Schwarz FSUP spectrum analyzer. TIMING CHARACTERISTICS AVDD = DVDD = VP = 3.0 V, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter Limit Unit Test Conditions/Comments t 1 10 ns min DATA to CLK setup time t 2 10 ns min DATA to CLK hold time t 3 25 ns min CLK high duration t 4 25 ns min CLK low duration t 5 10 ns min CLK to LE setup time t 6 20 ns min LE pulse width Figure 2. Timing Diagram CLK DB22 DB2 DATA LE t1 LE DB23 (MSB) t2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t3 t4 t6 t5 |
Ähnliche Teilenummer - ADF41020 |
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Ähnliche Beschreibung - ADF41020 |
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