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ACE93C56DP+TH Datenblatt(PDF) 8 Page - ACE Technology Co., LTD.

Teilenummer ACE93C56DP+TH
Bauteilbeschribung  Three-wire Serial EEPROM
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Hersteller  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

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ACE93C46.56.66
Three-wire Serial EEPROM
VER 1.5
8
WRITE (WRITE):
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The
self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A
logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part is ready for further
instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed
programming cycle, TWP.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction programs every bit in the m
emory array to the logic “1” state and is primarily used for
testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (TCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction.
The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250ns
(TCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming
modes and should be executed after all programming operations. The operation of the Read instruction is independent
of both the EWEN and EWDS instructions and can be executed at any time.
Timing Diagrams
Note: This is the minimum SK period.
Figure 1: Synchronous Data Timing


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