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AD5206BN10 Datenblatt(PDF) 9 Page - Analog Devices |
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AD5206BN10 Datenblatt(HTML) 9 Page - Analog Devices |
9 / 11 page AD5204/AD5206 –9– REV. 0 The typical distribution of RBA from channel-to-channel matches within ±1%. However, device-to-device matching is process lot dependent, having a ±30% variation. The change in R BA with temperature has a 700 ppm/ °C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting A terminal to +5 V and B terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to termi- nals AB is: VW (Dx) = Dx/256 × V AB + VB (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore, the drift improves to 15 ppm/ °C. D7 D0 A1 W1 B1 VDD AD5204/AD5206 CS CLK 8 EN ADDR DEC A2 A1 A0 SDI DI SER REG D0 D7 A4/A6 W4/W6 B4/B6 SHDN RDAC LATCH #1 R D7 D0 RDAC LATCH #4/#6 R SDO DO GND PR (AD5204 ONLY) (AD5204 ONLY) (AD5204 ONLY) Figure 17. Block Diagram DIGITAL INTERFACING The AD5204/AD5206 contain a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. Figure 17 shows more detail of the internal digital circuitry. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table IV. When using a positive (VDD) and negative (VSS) supply voltage, the logic levels are still referenced to digital ground (GND). The serial-data-output (SDO) pin contains an open drain n- channel FET. This output requires a pull-up resistor in order to transfer data to the next package’s SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply of the AD5204 SDO output device, e.g., the AD5204 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining several RDACs from a single processor serial-data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be ac- counted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every pack- age are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding loca- tion. This would require 22 bits of address and data complying to the word format provided in Table I if two AD5204 four- channel RDACs are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. See Figure 19 for equivalent SDO output circuit schematic. Table IV. Input Logic Control Truth Table CLK CS PR SHDN Register Activity L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the SDI pin. The eleventh previously entered bit is shifted out of the SDO pin. X P H H Load SR data into RDAC latch based on A2, A1, A0 decode (Table V). X H H H No Operation. X X L H Sets all RDAC latches to midscale, wiper centered and SDO latch cleared. X H P H Latches all RDAC latches to 80H. X H H L Open circuits all Resistor A termi- nals, connects W to B, turns off SDO output transistor. NOTE: P = positive edge, X = don’t care, SR = shift register. Table V. Address Decode Table A2 A1 A0 Latch Decoded 0 0 0 RDAC#1 0 0 1 RDAC#2 0 1 0 RDAC#3 0 1 1 RDAC#4 1 0 0 RDAC#5 AD5206 Only 1 0 1 RDAC#6 AD5206 Only The data setup and data hold times in the specification table determine the data valid time requirements. The last 11 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder enabling one of four or six positive edge triggered RDAC latches, see Figure 18 detail. |
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Ähnliche Beschreibung - AD5206BN10 |
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