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AD734BN Datenblatt(PDF) 9 Page - Analog Devices |
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AD734BN Datenblatt(HTML) 9 Page - Analog Devices |
9 / 12 page AD734 –9– REV. C A PRECISION AGC LOOP The variable denominator of the AD734 and its high gain- bandwidth product make it an excellent choice for precise automatic gain control (AGC) applications. Figure 13 shows a suggested method. The input signal, EIN, which may have a peak amplitude of from 10 mV to 10 V at any frequency from 100 Hz to 10 MHz, is applied to the X input, and a fixed posi- tive voltage EC to the Y input. Op amp A2 and capacitor C2 form an integrator having a current summing node at its invert- ing input. (The AD712 dual op amp is a suitable choice for this application.) In the absence of an input, the current in D2 and R2 causes the integrator output to ramp negative, clamped by diode D3, which is included to reduce the time required for the loop to establish a stable, calibrated, output level once the circuit has received an input signal. With no input to the denominator (U0 and U2), the gain of the AD734 is very high (about 70 dB), and thus even a small input causes a substantial output. EOUT D3 1N914 R2 1M R1 1M C1 1 F EIN R3 1M OP AMP = AD712 DUAL 1 2 3 4 5 6 7 10 8 9 11 13 12 14 W ER VN VP DD Z1 Z2 X1 X2 U1 U2 U0 Y1 Y2 AD734 L 0.1 F 0.1 F +15V –15V A1 NC C2 1 F A2 D2 1N914 +1V TO +10V EC D1 1N914 C1 1 F L Figure 13. Precision AGC Loop Diode D1 and C1 form a peak detector, which rectifies the out- put and causes the integrator to ramp positive. When the current in R1 balances the current in R2, the integrator output holds the denominator output at a constant value. This occurs when there is sufficient gain to raise the amplitude of EIN to that required to establish an output amplitude of EC over the range of +1 V to +10 V. The X input of the AD734, which has finite offset voltage, could be troublesome at the output at high gains. The output offset is reduced to that of the X input (one or two millivolts) by the offset loop comprising R3, C3, and buffer A1. The low pass corner frequency of 0.16 Hz is transformed to a high-pass corner that is multiplied by the gain (for example, 160 Hz at a gain of 1000). In applications not requiring operation down to low frequencies, amplifier A1 can he eliminated, but the AD734’s input resistance of 50 k Ω between X1 and X2 will reduce the time constant and increase the input offset. Using a non-polar 20 µF tantalum capacitor for C1 will result in the same unity-gain high-pass corner; in this case, the offset gain increases to 20, still very acceptable. Figure 14 shows the error in the output for sinusoidal inputs at 100 Hz, 100 kHz, and 1 MHz, with EC set to +10 V. The out- put error for any frequency between 300 Hz and 300 kHz is similar to that for 100 kHz. At low signal frequencies and low input amplitudes, the dynamics of the control loop determine the gain error and distortion; at high frequencies, the 200 MHz gain-bandwidth product of the AD734 limit the available gain. The output amplitude tracks EC over the range +1 V to slightly more than +10 V. +2 +1 0 –1 –2 10m 100m 1 10 INPUT AMPLITUDE – Volts 100kHZ 100HZ 1MHZ Figure 14. AGC Amplifier Output Error vs. Input Voltage WIDEBAND RMS-DC CONVERTER USING U INTERFACE The AD734 is well suited to such applications as implicit RMS- DC conversion, where the AD734 implements the function V RMS = avg V IN 2 [] V RMS (13) using its direct divide mode. Figure 15 shows the circuit. L 1/2 AD708 VIN 2 V O = V O R1 3.32k VIN 1 2 3 4 5 6 7 10 8 9 11 13 12 14 W ER VN VP DD Z1 Z2 X1 X2 U1 U2 U0 Y1 Y2 AD734 0.1 F 0.1 F +15V –15V U2a C1 47 F U1 L L L C2 1 F L L L 1/2 AD708 U2b Figure 15. A 2-Chip, Wideband RMS-DC Converter In this application, the AD734 and an AD708 dual op amp serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth. Figure 16 shows the circuit’s performance for square-, sine-, and triangle-wave inputs. The circuit accepts signals as high as 10 V p-p with a crest factor of 1 or 1 V p-p with a crest factor of 10. The circuit’s response is flat to 10 MHz with an input of 10 V, flat to almost 5 MHz for an input of 1 V, and to almost 1 MHz for inputs of 100 mV. For accurate measurements of input levels below 100 mV, the AD734’s output offset (Z inter- face) voltage, which contributes a dc error, must be trimmed out. In Figure 15’s circuit, the AD734 squares the input signal, and its output (VIN 2) is averaged by a low-pass filter that consists of R1 and C1 and has a corner frequency of 1 Hz. Because of the implicit feedback loop, this value is both the output value, VRMS, and the denominator in Equation (13). U2a and U2b, an AD708 dual dc precision op amp, serve as unity-gain buffers, supplying both the output voltage and driving the U interface. |
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