Datenblatt-Suchmaschine für elektronische Bauteile |
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AD7476SRT Datenblatt(PDF) 5 Page - Analog Devices |
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AD7476SRT Datenblatt(HTML) 5 Page - Analog Devices |
5 / 20 page REV. D AD7476/AD7477/AD7478 –5– TIMING SPECIFICATIONS1, 2 (V DD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX AD7476/AD7477/AD7478 Parameter 3 V 3 5V 3 Unit Description fSCLK 4 10 10 kHz min 20 20 MHz max A Version 12 12 MHz max B Version tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum Quiet Time Required between Bus Relinquish and Start of Next Conversion t1 10 10 ns min Minimum CS Pulsewidth t2 10 10 ns min CS to SCLK Setup Time t3 5 20 20 ns max Delay from CS until SDATA Three-State Disabled t4 5 40 20 ns max Data Access Time after SCLK Falling Edge, A Version 70 20 ns max Data Access Time after SCLK Falling Edge, B Version t5 0.4 × t SCLK 0.4 × t SCLK ns min SCLK Low Pulsewidth t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK High Pulsewidth t7 10 10 ns min SCLK to Data Valid Hold Time t8 6 10 10 ns min SCLK Falling Edge to SDATA High Impedance 25 25 ns max SCLK Falling Edge to SDATA High Impedance tPOWER-UP 7 11 µs typ Power-Up Time from Full Power-Down NOTES 1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version. 33 V specifications apply from V DD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from V DD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 4Mark/Space ratio for the SCLK input is 40/60 to 60/40. 5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 6t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 7See Power-Up Time section. Specifications subject to change without notice. 200 A IOL 200 A IOH CL 50pF TO OUTPUT PIN 1.6V Figure 1. Load Circuit for Digital Output Timing Specifications |
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