–5–

REV. D

AD7701

TIMING CHARACTERISTICS

1, 2

Parameter

(A, B Versions)

(S, T Versions)

Units

Conditions/Comments

3, 4

200

200

kHz min

Master Clock Frequency: Internal Gate Oscillator

5

5

MHz max Typically 4.096 MHz

200

200

kHz min

Master Clock Frequency: Externally Supplied

5

5

MHz max

5

50

50

ns max

Digital Output Rise Time. Typically 20 ns

5

50

50

ns max

Digital Output Fall Time. Typically 20 ns

0

0

ns min

SC1, SC2 to CAL High Setup Time

50

50

ns min

SC1, SC2 Hold Time After CAL Goes High

6

1000

1000

ns min

SLEEP

High to CLKIN High Setup Time

SSC Mode

7

ns max

Data Access Time (CS Low to Data Valid)

100

100

ns max

SCLK Falling Edge to Data Valid Delay (25 ns typ)

250

250

ns min

MSB Data Setup Time. Typically 380 ns

300

300

ns max

SCLK High Pulse Width. Typically 240 ns

790

790

ns max

SCLK Low Pulse Width. Typically 730 ns

8

ns max

8, 9

ns max

CS

High to Hi-Z Delay

SEC Mode

5

5

MHz

Serial Clock Input Frequency

35

35

ns min

SCLK Input High Pulse Width

160

160

ns min

SCLK Low Pulse Width

7, 10

160

160

ns max

Data Access Time (CS Low to Data Valid). Typically 80 ns

11

150

150

ns max

SCLK Falling Edge to Data Valid Delay. Typically 75 ns

8

250

250

ns max

CS

High to Hi-Z Delay

8

200

200

ns max

SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

AC Mode

40

40

ns min

CS

Setup Time. Typically 20 ns

180

180

ns max

Data Delay Time. Typically 90 ns

200

200

ns max

SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

NOTES

°C to ensure compliance. All input signals are specified with t

draw higher current than specified and possibly become uncalibrated.

then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the

true bus relinquish time of the part and as such as independent of external bus loading capacitance.

great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than

4 CLKIN cycles plus 160 ns after CS goes low.

10%; AGND = DGND = O V;