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AD7707BR Datenblatt(PDF) 8 Page - Analog Devices

Teilenummer AD7707BR
Bauteilbeschribung  3 V/5 V, -10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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REV. A
AD7707
–8–
Pin No.
Mnemonic
Function
14
REF IN(–)
Reference Input. Negative input of the differential reference input to the AD7707. The
REF IN(–) can lie anywhere between AVDD and AGND provided REF IN(+) is greater than
REF IN(–).
15
AGND
Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
16
DRDY
Logic Output. A logic low on this output indicates that a new output word is available from the
AD7707 data register. The DRDY pin will return high upon completion of a read operation of a
full output word. If no data read has taken place between output updates, the DRDY line will
return high for 500
× t
CLK IN cycles prior to the next output update. While DRDY is high, a read
operation should neither be attempted nor in progress to avoid reading from the data register as
it is being updated. The DRDY line will return low again when the update has taken place.
DRDY is also used to indicate when the AD7707 has completed its on-chip calibration
sequence.
17
DOUT
Serial Data Output with serial data being read from the output shift register on the part. This
output shift register can contain information from the setup register, communications register,
clock register or data register, depending on the register selection bits of the Communications
Register.
18
DIN
Serial Data Input with serial data being written to the input shift register on the part. Data from
this input shift register is transferred to the setup register, clock register or communications
register, depending, on the register selection bits of the Communications Register.
19
DVDD
Digital Supply Voltage, +2.7 V to +5.25 V operation.
20
DGND
Ground reference point for the AD7707’s internal digital circuitry.
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION)
Table I shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and –3 dB
frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges
with a VREF of +2.5 V and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table II
shows the rms noise and peak-to-peak resolution when operating in unbuffered mode. It is important to note that the peak-to-peak num-
bers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The
numbers given are for bipolar input ranges with a VREF of +2.5 V. These numbers are typical and are rounded to the nearest LSB.
The numbers apply for the CLK DIV bit of the Clock Register set to 0. The output noise comes from two sources. The first is the
electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of fre-
quency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise
source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the
same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of
resolution.
Table I. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN1 and AIN2 Unbuffered Mode Only
Filter First
Typical Output RMS Noise in
V
(Peak-to-Peak Resolution in Bits)
Notch and O/P
–3 dB
Gain of
Gain of
Gain of
Gain of
Gain of
Gain of
Gain of
Gain of
Data Rate
Frequency
1
2
4
8
16
32
64
128
MCLK IN = 2.4576 MHz
10 Hz
2.62 Hz
1.2 (16)
0.7 (16)
0.7 (16)
0.54 (16)
0.28 (16)
0.28 (16)
0.28 (15.5) 0.27 (14.5)
50 Hz
13.1 Hz
3.6 (16)
2.1 (16)
1.25 (16)
0.89 (16)
0.62 (16)
0.60 (15.5) 0.56 (14.5) 0.56 (13.5)
60 Hz
15.72 Hz
4.7 (16)
2.6 (16)
1.5 (16)
0.94 (16)
0.73 (16)
0.68 (15.5) 0.66 (14.5) 0.63 (13.5)
250 Hz
65.5 Hz
95 (13)
65 (13)
23.4 (13)
11.6 (13)
6.5 (13)
3.4 (13)
2.1 (12.5)
1.5 (12)
500 Hz
131 Hz
600 (10.5) 316 (10.5) 138 (10.5)
71 (10.5)
38 (10.5)
18 (10.5)
10 (10)
5.7 (10)
MCLK IN = 1 MHz
4.05 Hz
1.06 Hz
1.19 (16)
0.69 (16)
0.71 (16)
0.63 (16)
0.27 (16)
0.27 (16)
0.26 (15.5) 0.24 (15)
20 Hz
5.24 Hz
3.68 (16)
2.18 (16)
1.19 (16)
0.94 (16)
0.6 (16)
0.6 (15.5)
0.56 (14.5) 0.56 (13.5)
25 Hz
6.55 Hz
4.78 (16)
2.66 (16)
1.51 (16)
1.07 (16)
0.7 (16)
0.67 (15.5) 0.66 (14.5) 0.65 (13.5)
100 Hz
26.2 Hz
100 (13)
50.1 (13)
23.5 (13)
11.9 (13)
5.83 (13)
3.64 (13)
2.16 (12.5) 1.5 (12)
200 Hz
52.5 Hz
543 (10.5) 318 (10.5) 132 (10.5)
68.1 (10.5) 33.1 (10.5) 17.6 (10.5) 9.26 (10.5) 6.13 (10)


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