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AD7821BQ Datenblatt(PDF) 10 Page - Analog Devices |
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AD7821BQ Datenblatt(HTML) 10 Page - Analog Devices |
10 / 12 page AD7821 REV. A –10– MICROPROCESSOR INTERFACING The AD7821 is designed for easy interfacing to microprocessors as a memory mapped peripheral or an I/O device. This reduces to a minimum the amount of external logic required for interfacing. AD7821 – 68008 INTERFACE Figure 14 shows an AD7821 interface to the 68008 micropro- cessor. The ADC is configured for the RD interface mode. This means that one read instruction starts a conversion and reads the result when the conversion is completed. The read cycle is stretched out over the entire conversion period by taking the INT line back to the DTACK input of the 68008. Starting a conversion and reading the relevant data consists of a <MOVE B Dn, addr> instruction, where addr is the decoded ADC ad- dress and Dn is the data register into which the result is placed. Figure 14. AD7821 to 68008 Interface AD7821 – 8088 INTERFACE A typical interface to the 8088 is shown in Figure 15. The AD7821 is configured for the RD interface mode. One read in- struction starts a conversion and reads the result. The read cycle is stretched out over the entire conversion period by taking the RDY line back to the READY input of the 8088. Starting a con- version and reading the result consists of a <MOV AX, (addr)> instruction, where addr is the decoded ADC address and AX is the 8088 data register into which the conversion result is placed. Figure 15. AD7821 to 8088 Interface AD7821 – TMS32010 INTERFACE A typical interface to the TMS32010 is shown in Figure 16. The AD7821 is mapped at a port address and the interface is designed for the maximum TMS32010 clock frequency of 20 MHz. In this case, the AD7821 is configured in the WR-RD interface mode. This means that a write instruction starts a conversion and a read instruction reads the result when the conversion is com- pleted. A precise timer or clock source is used to start a conver- sion in applications requiring equidistant sampling intervals. The scheme used, whereby the AD7821 generates an interrupt to the TMS32010, is limited in that it does not allow the AD7821 to be sampled at its maximum rate. This is because the time between samples has to be long enough to allow the TMS32010 to service its interrupt and read data from the AD7821. Constant interruption of the TMS32010 by the AD7821, every time the ADC completes a conversion, is not a very efficient use of the processor time. To overcome these problems, some buffer memory or FIFO could be placed be- tween the AD7821 and the TMS32010. The INT line of the AD7821 could be used to trigger a pulse which drives its CS and RD lines and places the AD7821 data into a FIFO or buffer memory. The microprocessor can then read a batch of data from the FIFO or buffer memory at some convenient time. Reading data from the AD7821, after an INT has been re- ceived, consists of <IN A, PA> instruction (PA is the decoded ADC address). Figure 16. AD7821 to TMS32010 Interface AD7821 – 8051 INTERFACE Figure 17 shows the AD7821 interface to the 8051 microcom- puter. The AD7821 is configured in the WR-RD interface mode and is connected to the 8051 ports. The processor starts conver- sion and then polls INT, until it goes low, before reading the conversion result. Data is read from the AD7821 by using the <MOV A, 90H> instruction (90H is the address for Port 1). Figure 17. AD7821 to 8051 Interface |
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