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AD7825BR Datenblatt(PDF) 10 Page - Analog Devices |
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AD7825BR Datenblatt(HTML) 10 Page - Analog Devices |
10 / 20 page AD7822/AD7825/AD7829 –10– REV. B CONVST DB0–DB7 A0–A2 EOC CS RD t2 t1 t3 t13 VALID DATA ADDRESS CHANNEL y TRACK CHx TRACK CHx HOLD CHx TRACK CHy HOLD CHy 120ns Figure 12. Channel Hopping Timing There is a minimum time delay between the falling edge of RD and the next falling edge of the CONVST signal, t13. This is the minimum acquisition time required of the track-and-hold in order to maintain 8-bit performance. Figure 13 shows the typical performance of the AD7825 when channel hopping for various acquisition times. These results were obtained using an external reference and internal VMID while channel hopping between VIN1 and VIN4 with 0 V on Channel 4 and 0.5 V on Channel 1. ACQUISITION TIME – ns 8.0 5.0 500 10 200 100 50 40 30 20 15 7.5 7.0 6.5 6.0 5.5 8.5 Figure 13. Effective Number of Bits vs. Acquisition Time for the AD7825 The on-chip track-and-hold can accommodate input frequen- cies to 10 MHz, making the AD7822, AD7825, and AD7829 ideal for subsampling applications. When the AD7825 is con- verting a 10 MHz input signal at a sampling rate of 2 MSPS, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dBs as shown in Figure 14. INPUT FREQUENCY – MHz 50 38 0.2 10 1 3 4 568 48 46 44 42 40 fSAMPLE = 2MHz Figure 14. SNR vs. Input Frequency on the AD7825 POWER-UP TIMES The AD7822/AD7825/AD7829 have a 1 µs power-up time when using an external reference and a 25 µs power-up time when using the on-chip reference. When VDD is first connected, the AD7822, AD7825, and AD7829 are in a low current mode of operation. Ensure that the CONVST line is not floating when VDD is applied, as if there is a glitch on CONVST while VDD is rising, the part will attempt to power up before VDD has fully settled and could enter an unknown state. In order to carry out a conversion, the AD7822, AD7825, and AD7829 must first be powered up. The AD7829 is powered up by a rising edge on the CONVST pin and a conversion is initiated on the falling edge of CONVST. Figure 15 shows how to power up the AD7829 when VDD is first connected or after the AD7829 has been powered down using the CONVST pin when using either the on-chip, or an external, reference. When using an external reference, the falling edge of CONVST may occur before the required power-up time has elapsed; however, the conversion will not be initiated on the falling edge of CONVST but rather at the moment when the part has completely powered up, i.e., after 1 µs. If the falling edge of CONVST occurs after the required power-up time has elapsed, then it is upon this falling edge that a conversion is initiated. When using the on-chip reference, it is nec- essary to wait the required power-up time of approximately 25 µs before initiating a conversion; i.e., a falling edge on CONVST may not occur before the required power-up time has elapsed, when VDD is first connected or after the AD7829 has been powered down using the CONVST pin as shown in Figure 15. VDD tPOWER-UP 1 s CONVST VDD CONVST tPOWER-UP 25 s CONVERSION INITIATED HERE CONVERSION INITIATED HERE EXTERNAL REFERENCE ON-CHIP REFERENCE Figure 15. AD7829 Power-Up Time |
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