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AD7896SQ Datenblatt(PDF) 8 Page - Analog Devices |
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AD7896SQ Datenblatt(HTML) 8 Page - Analog Devices |
8 / 12 page REV. B –8– AD7896 Serial Interface The serial interface to the AD7896 consists of just three wires, a serial clock input (SCLK) and the serial data output (SDATA) and a conversion status output (BUSY). This allows for an easy-to-use interface to most microcontrollers, DSP processors and shift registers. Figure 4 shows the timing diagram for the read operation to the AD7896. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked out from the SDATA line on the falling edge of this clock and is valid on both the rising and falling edges of SCLK. The advantage of having the data valid on both the rising and falling edges of the SCLK is so that it gives the user greater flexibility in interfacing to the part and also so that a wider range of microprocessor and microcontroller interfaces can be accommodated. This also ex- plains the two timing figures t4 and t5 that are quoted on the dia- gram. The time t4 specifies how long after the falling edge of the SCLK that the next data bit becomes valid whereas the time t5 specifies how long after the falling edge of the SCLK that the current data bit is valid for. The first leading zero is clocked out on the first rising edge of SCLK, and note that the first zero may be valid on the first falling edge of SCLK even though the data access time is specified at 60 ns (5 V, A, B, J Versions only) for the other bits ( and the SCLK high time will be 50 ns with a 10 MHz SCLK ). The reason that the first bit will be clocked out faster than the other bits is due to the internal architecture of the part. Sixteen clock pulses must be provided to the part to access to full conversion result. The AD7896 provides four lead- ing zeros followed by the 12-bit conversion result starting with the MSB (DB11). The last data bit to be clocked out on the penultimate falling clock edge is the LSB (DB0). On the six- teenth falling edge of SCLK the LSB (DB0) will be valid for a specified time to allow the bit to be read on the falling edge of the SCLK, and then the SDATA line is disabled (three-stated). After this last bit has been clocked out, the SCLK input should remain low until the next serial data read operation. If there are extra clock pulses after the sixteenth clock, the AD7896 will start over again with outputting data from its output register, and the data bus will no longer be three-stated even when the clock stops. Provided the serial clock has stopped before the next falling edge of CONVST, the AD7896 will continue to op- erate correctly with the output shift register being reset on the falling edge of CONVST. However, the SCLK line must be low when CONVST goes low in order to reset the output shift register correctly. The serial clock input does not need to be continuous during the serial read operation. The sixteen bits of data (four leading zeros and 12-bit conversion result) can be read from the AD7896 in a number of bytes. However, the SCLK input must remain low between the two bytes. The maximum SCLK frequency will be 10 MHz for 5 V opera- tion (giving a throughput of 100 kHz) and at 2.7 V the maxi- mum SCLK frequency will be less than 10 MHz to allow for the longer data access time, t4 (60 ns @ 5 V, 100 ns @ 2.7 V (A, B, J Versions) 70 ns @ 5 V, (110 ns @ 2.7 V (S Version)). Note that at 3.0 V operation (A, B, J Versions) an SCLK of 10 MHz (throughput rate of 100 kHz) may be acceptable if the required processor setup time is 0 ns (this may be possible with an ASIC or FPGA). The data must be read in the next 10 ns which is specified as the data hold time, t5, after the SCLK edge. The AD7896 counts the serial clock edges to know which bit from the output register should be placed on the SDATA out- put. To ensure that the part does not lose synchronization, the serial clock counter is reset on the falling edge of the CONVST input provided the SCLK line is low. The user should ensure that a falling edge on the CONVST input does not occur while a serial data read operation is in progress. MICROPROCESSOR/MICROCONTROLLER INTERFACE The AD7896 provides a three-wire serial interface that can be used for connection to the serial ports of DSP processors and microcontrollers. Figures 5 through 8 show the AD7896 inter- faced to a number of different microcontrollers and DSP pro- cessors. The AD7896 accepts an external serial clock and as a result, in all interfaces shown here, the processor/controller is configured as the master, providing the serial clock, with the AD7896 configured as the slave in the system. AD7896–8051 Interface Figure 5 shows an interface between the AD7896 and the 8X51/ L51 microcontroller. The 8X51/L51 is configured for its Mode 0 serial interface mode. The diagram shows the simplest form of the interface where the AD7896 is the only part connected to the serial port of the 8X51/L51 and, therefore, no decoding of the serial read operations is required. t2 4 LEADING ZEROS DOUT (O/P) SCLK (I/P) t6 1 2 3 4 5 6 15 16 DB0 DB10 DB11 3-STATE t5 t3 t4 3-STATE t2 = t3 = 40ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 50ns MAX @ 5v, A, B, VERSIONS Figure 4. Data Read Operation |
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