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AD808-622BRRL Datenblatt(PDF) 7 Page - Analog Devices |
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AD808-622BRRL Datenblatt(HTML) 7 Page - Analog Devices |
7 / 12 page AD808 REV. 0 –7– THEORY OF OPERATION Quantizer The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with common- mode voltage as high as the positive supply. The input offset voltage is factory trimmed and is typically less than 1 mV. XFCB’s dielectric isolation allows the different blocks within this mixed- signal IC to be isolated from each other, hence the 4 mV Sensi- tivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD808 quantizer toggles at 2 mV (4.0 mV sensitivity) at the input without making bit errors. When the input signal is low- ered below 2 mV, circuit performance is dominated by input noise, and not crosstalk. Signal Detect The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a posi- tive and a negative peak detector. The threshold value is sub- tracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis. POSITIVE PEAK DETECTOR NEGATIVE PEAK DETECTOR LEVEL SHIFT DOWN LEVEL SHIFT UP THRESHOLD BIAS PIN NIN SDOUT IHYS + + AD808 COMPARATOR STAGES & CLOCK RECOVERY PLL ITHR Figure 11. Signal Level Detect Circuit Block Diagram Phase-Locked Loop The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 12 for a block dia- gram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. VCO RETIMING DEVICE DET FDET DATA INPUT 1 S S + 1 RECOVERED CLOCK OUTPUT RETIMED DATA OUTPUT Figure 12. PLL Block Diagram The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data fre- quency and the VCO frequency. With a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. However, with random data, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the fre- quency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 2 7–1 pseu- dorandom code is 1/2 degree, and this is small compared to random jitter. The jitter bandwidth for the PLL is 0.06% of the center fre- quency. This figure is chosen so that sinusoidal input jitter at 350 Hz will be attenuated by 3 dB. The damping ratio of the PLL is user programmable with a single external capacitor. At 622 MHz, a damping ratio of 5 is obtained with a 0.47 µF capacitor. More generally, the damping ratio scales as (fDATA × C D) 1/2. A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisi- tion time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop band- width of the PLL and is independent of the damping ratio. In practice the acquisition time is dominated by the frequency acquisition. The fractional loop bandwidth of 0.06% should give an acquisition time of 2000 bit periods. However, the actual acquisition time is several million bit periods and is comprised mostly of the time needed to slew the voltage on the damping capacitor to final value. |
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